TMS320VC5502

Fixed-Point Digital Signal Processor

www.ti.com

SPRS166J –APRIL 2001 –REVISED AUGUST 2006

3.14.3IPORT Interface

The IPORT interfaces the I-Cache to the EMIF module. The ICACHETO bit of the IPORT Bus Error Register (IERR) can be used to determine if a time-out error has occurred during an ICACHE access to external memory. The time-out feature is enabled through the EMIFTOEN bit of the Time-Out Control Register (TOCR).

The IPORT can be placed into idle through the IPORTI bit of the Idle Control Register (ICR) and executing the IDLE instruction. The IPORT will go into idle when there are no new requests from the ICACHE. When the IPORT is in idle, it will stop accepting new requests from the CPU, it is important that the program flow not use external memory in this case. If there are requests from the CPU, the IPORT will not respond and hang. The ICR register will generate a bus error if the IPORT is idled without the CPU domain being in idle.

3.14.3.1 IPORT Bus Error Register (IERR)

The IPORT Bus Error Register bit layout is shown in Figure 3-48 and the bits are described in Table 3-53.

R, 00000000

LEGEND: R = Read, W = Write, n = value at reset

Figure 3-48. IPORT Bus Error Register Layout (0x0302)

Table 3-53. IPORT Bus Error Register Bit Field Description

TMS320VC5502

Fixed-Point Digital Signal Processor

www.ti.com

SPRS166J –APRIL 2001 –REVISED AUGUST 2006

3.14.4System Configuration Register (CONFIG)

The System Configuration Register can be used to determine the operational state of the ICACHE. If the ICACHE is not functioning, the CACHEPRES bit of the CONFIG register will be cleared. If the ICACHE is functioning normally, this bit will be set.

The System Configuration Register bit layout is shown in Figure 3-49 and the bits are described in Table 3-54.

LEGEND: R = Read, W = Write, n = value at reset

(1)This Reserved bit must be kept as zero during any writes to CONFIG.

Figure 3-49. System Configuration Register Layout (0x07FD)

Table 3-54. System Configuration Register Bit Field Description

(1)This Reserved bit must be kept as zero during any writes to CONFIG.

TMS320VC5502

Fixed-Point Digital Signal Processor

www.ti.com

SPRS166J –APRIL 2001 –REVISED AUGUST 2006

3.14.5Time-Out Control Register (TOCR)

The Time-Out Control Register can be used to select whether or not a time-out error is generated when an access to a disabled/idled peripheral module occurs. If the CPU or DMA access a disabled/idle peripheral module and 512 CPU clock cycles pass without an acknowledgement from the peripheral module, then a time-out error will be sent to the corresponding module if bit 1 in the Time-Out Control Register is set. A time-out error will generate a CPU bus error that can be serviced through software by using the bus error interrupt (BERR) (see Section 3.17, Interrupts, for more information on interrupts). If the DMA gets a time-out error, it will set the TIMEOUT bit in the DMA Status Register (DMACSR) and generate a time-out error that can be serviced through software by the CPU [see the

TMS320VC5501/5502 DSP Direct Memory Access (DMA) Controller Reference Guide (literature number SPRU613) for more information on using this feature of the DMA].

The Time-Out Control Register can also be used to select whether or not a time-out error is generated when a memory access through the EMIF module stalls for more than 512 CPU clock cycles. It is recommended that this feature not be used for it can cause unexpected results.

∙ PERITOEN = 1: A time-out error is generated when a CPU access to a disabled/idle peripheral module stalls for more than 512 CPU clock cycles.