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1 TMS320VC5502

1.1Features

∙High-Performance, Low-Power, Fixed-Point TMS320C55x™ Digital Signal Processor (DSP)

–3.33-/5-ns Instruction Cycle Time

–300-/200-MHz Clock Rate

–16K-Byte Instruction Cache (I-Cache)

–One/Two Instructions Executed per Cycle

–Dual Multipliers [Up to 600 Million Multiply-Accumulates Per Second (MMACS)]

–Two Arithmetic/Logic Units (ALUs)

–One Program Bus, Three Internal Data/Operand Read Buses, and Two Internal Data/Operand Write Buses

∙Instruction Cache (16K Bytes)

∙32K x 16-Bit On-Chip RAM That is Composed of Eight Blocks of 4K × 16-Bit Dual-Access RAM (DARAM) (64K Bytes)

∙16K × 16-Bit One-Wait-State On-Chip ROM (32K Bytes)

∙8M × 16-Bit Maximum Addressable External Memory Space

∙32-Bit External Parallel Bus Memory Supporting External Memory Interface (EMIF) With General-Purpose Input/Output (GPIO) Capabilities and Glueless Interface to:

–Asynchronous Static RAM (SRAM)

–Asynchronous EPROM

–Synchronous DRAM (SDRAM)

–Synchronous Burst RAM (SBRAM)

∙Emulation/Debug Trace Capability Saves Last 16 Program Counter (PC) Discontinuities and Last 32 PC Values

∙Programmable Low-Power Control of Six Device Functional Domains

TMS320VC5502

Fixed-Point Digital Signal Processor

SPRS166J –APRIL 2001 –REVISED AUGUST 2006

∙On-Chip Peripherals

–Six-Channel Direct Memory Access (DMA) Controller

–Three Multichannel Buffered Serial Ports (McBSPs)

–Programmable Analog Phase-Locked Loop (APLL) Clock Generator

–General-Purpose I/O (GPIO) Pins and a Dedicated Output Pin (XF)

–8-Bit/16-Bit Parallel Host-Port Interface (HPI)

–Four Timers

∙Two 64-Bit General-Purpose Timers

∙64-Bit Programmable Watchdog Timer

∙64-Bit DSP/BIOS™ Counter

–Inter-Integrated Circuit (I2C) Interface

–Universal Asynchronous Receiver/ Transmitter (UART)

∙On-Chip Scan-Based Emulation Logic

∙IEEE Std 1149.1(1) (JTAG) Boundary Scan

Logic

∙Packages:

–176-Terminal LQFP (Low-Profile Quad Flatpack) (PGF Suffix)

–201-Terminal MicroStar BGA™ (Ball Grid Array) (GZZ and ZZZ Suffixes)

∙3.3-V I/O Supply Voltage

∙1.26-V Core Supply Voltage

(1)IEEE Standard 1149.1 - 1990 Standard Test Access Port and Boundary Scan Architecture