3 Functional Overview

TCK

C55x CPU

ECLKIN

TMS

Data

ECLKOUT1

TDI

Instruction Buffer

Program Flow

Address Data Flow

ECLKOUT2

Emulation Control

Computation

TDO

Unit (IU)

Unit (PU)

Unit (AU)

EMIFCLKS

Unit (DU)

TRST

EMU0

EMU1/OFF

Program Address Bus

[PAB]

(24)

External

Program Data Bus [PB] (32)

Memory

Interface

Data Read Address Bus B [BAB] (24)

(EMIF)

Data Read Bus B [BB] (16)

A[21:2]

Parallel

A[21:2]

D[31:0]

Port MUX

D[31:0]

C[15:0]

C[15:0]

Data Read Address Bus C [CAB] (24)

Data Read Bus C [CB] (16)

Data Read Address Bus D [DAB] (24)

Data Read Bus D [DB] (16)

Data Write Address Bus E [EAB] (24)

Data Write Bus E [EB] (16)

PGPIO[35:0]

Data Write Address Bus F [FAB] (24)

PGPIO[45:36]

Host Port

HD[7:0]

Data Write Bus F [FB] (16)

Parallel

MUX

HC0

General−

HC1

Purpose I/O

TIM

Timer

XPORT

DARAM

ROM

Instruction

DPORT

Cache

HA[15:0]

HD[15:0]

X1

HAS

X2/CLKIN

Clock Generator

MPORT

IPORT

HBIL

HCNTL0

CLKOUT

Host−Port

HCNTL1

Interface (HPI)

HCS

Peripheral

HR/W

Power

Controller

Internal Memory

HDS1

Interface

HDS2

Management

HRDY

EMIF

DMA

Timer 3

HINT

DARAM0

HPIENA

WDTimer

DARAM1

Controller

(DSP/BIOS Timer)

PERI

General−Purpose

Muxing

I/O

NMI/WDTOUT

IO6 IO7

IO4 IO5

IO2 IO3

IO0 IO1

Logic

NMI

INT3

INT3

Interrupt

I2C

McBSP

McBSP2

TX

UART

RX

RESET

GPIO7

GPIO6

GPIO4

GPIO2

GPIO0 GPIO1

RESET Control

INT[2:0]

INT[2:0]

SCL

SDA

FSX

DX CLKR

CLKX

DR FSR

Serial Port 2 MUX

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Functional Overview

31