TMS320VC5502

Fixed-Point Digital Signal Processor

www.ti.com

SPRS166J –APRIL 2001 –REVISED AUGUST 2006

2.2Pin Assignments

2.2.1Ball Grid Array (GZZ and ZZZ)

The TMS320VC5502 is offered in two 201-terminal ball grid array (BGA) packages, both of which include 25 thermal balls to improve thermal dissipation. Except for their Eco-Status (refer to Section 6.2, Packaging Information), both packages are essentially the same. Figure 2-1 illustrates the ball locations for both BGA packages. Table 2-1 lists the locations of the thermal balls and Table 2-2 lists the signal names and terminal numbers.

NOTE

Some TMX samples were shipped in the GGW package. For more information on the

GGW package, see the TMS320VC5502 and TMS320VC5501 Digital Signal Processors

Silicon Errata (literature number SPRZ020D or later).

U

T

R

P

N

M

L

K

J

H

G

F

E

D

C

B

A

Figure 2-1. 201-Terminal GZZ and ZZZ Ball Grid Array (Bottom View)

Table 2-1. 201-Terminal GZZ and ZZZ Ball Grid Array Thermal Ball Locations(1)

(1)For best device thermal performance:

∙An array of 25 land pads must be added on the top layer of the PCB where the package will be mounted.

∙The PCB land pads should be the same diameter as the vias in the package substrate for optimal Board Level Reliability Temperature Cycle performance.

∙The land pads on the PCB should be connected together and to PCB through-holes. The PCB through-holes should in turn be connected to the ground plane for heat dissipation.

∙A solid internal plane is preferred for spreading the heat.

Refer to the MicroStar BGA™ Packaging Reference Guide (literature number SSYZ015) for guidance on PCB design, surface mount, and reliability considerations.

TMS320VC5502

Fixed-Point Digital Signal Processor

www.ti.com

SPRS166J –APRIL 2001 –REVISED AUGUST 2006

Table 2-2. 201-Terminal GZZ and ZZZ Ball Grid Array Ball Assignments(1)

(1)CVDD is core VDD, DVDD is I/O VDD, and PVDD is PLL VDD.

(2)NC = No Connect

TMS320VC5502

Fixed-Point Digital Signal Processor

www.ti.com

SPRS166J –APRIL 2001 –REVISED AUGUST 2006

2.2.2Low-Profile Quad Flatpack (PGF)

The TMS320VC5502 is offered in a 176-pin low-profile quad flatpack (LQFP). Figure 2-2 illustrates the pin locations for the 176-pin LQFP. Table 2-3 lists the signal names and pin numbers.

NOTE

TMS320VC5502PGF has completed Temp Cycle reliability qualification testing with no failures through 1500 cycles of –55°C to 125°C following an EIA/JEDEC Moisture Sensitivity Level 4 pre-condition at 220+5/–0°C peak reflow. Exceeding this peak reflow temperature condition or storage and handling requirements may result in either immediate device failure post-reflow, due to package/die material delamination ("popcorning"), or degraded Temp cycle life performance.

Please note that Texas Instruments (TI) also provides MSL, peak reflow and floor life information on a bar-code label affixed to dry-pack shipping bags. Shelf life, temperature and humidity storage conditions and re-bake instructions are prominently displayed on a nearby screen-printed label.

Figure 2-2. 176-Pin PGF Low-Profile Quad Flatpack (Top View)

TMS320VC5502

Fixed-Point Digital Signal Processor

www.ti.com

SPRS166J –APRIL 2001 –REVISED AUGUST 2006

Table 2-3. 176-Pin PGF Low-Profile Quad Flatpack Pin Assignments(1)

(1)CVDD is core VDD, DVDD is I/O VDD, and PVDD is PLL VDD.

(2)NC = No Connect