TMS320VC5502
Fixed-Point Digital Signal Processor
www.ti.com
SPRS166J –APRIL 2001 –REVISED AUGUST 2006
5.17 Inter-Integrated Circuit (I2C) Timings
Table 5-48 and Table 5-49 assume testing over recommended operating conditions (see Figure 5-47 and Figure 5-48).
Table 5-48. I2C Signals (SDA and SCL) Timing Requirements
NO.
IC1 tc(SCL)
IC2 tsu(SCLH-SDAL)
IC3 th(SCLL-SDAL)
IC4 
tw(SCLL)
IC5 tw(SCLH)
IC6 tsu(SDA-SCLH)
IC7 
th(SDA-SCLL)
IC8 tw(SDAH)
IC9 
tr(SDA)
IC10 tr(SCL)
IC11 
tf(SDA)
IC12 tf(SCL)
IC13 tsu(SCLH-SDAH)
IC14 
tw(SP)
IC15 Cb (4)
Cycle time, SCL
Setup time, SCL high before SDA low for a repeated START condition
Hold time, SCL low after SDA low for a START and a repeated START condition
Pulse duration, SCL low
Pulse duration, SCL high
Setup time, SDA valid before SCL high
Hold time, SDA valid after SCL low 
For I2C bus™ devices
Pulse duration, SDA high between STOP and START conditions
Rise time, SDA
Rise time, SCL
Fall time, SDA
Fall time, SCL
Setup time, SCL high before SDA high (for STOP condition)
Pulse duration, spike (must be suppressed)
Capacitive load for each bus line
VC5502-200
VC5502-300
Standard |
Fast |
|
UNIT |
|
Mode |
Mode |
|
|
|
MIN MAX |
MIN |
MAX |
|
|
10 |
|
2.5 |
|
µs |
4.7 |
|
0.6 |
|
µs |
4 |
|
0.6 |
|
µs |
4.7 |
|
1.3 |
|
µs |
4 |
|
0.6 |
|
µs |
250 |
100(1) |
|
ns |
|
0(2) |
0(2) |
0.9(3) |
µs |
|
4.7 |
|
1.3 |
|
µs |
1000 |
20 + 0.1C |
(4) |
300 |
ns |
|
|
b |
|
|
1000 |
20 + 0.1C |
(4) |
300 |
ns |
|
|
b |
|
|
300 |
20 + 0.1C |
(4) |
300 |
ns |
|
|
b |
|
|
300 |
20 + 0.1C |
(4) |
300 |
ns |
|
|
b |
|
|
4.0 |
|
0.6 |
|
µs |
|
|
0 |
50 |
ns |
400 |
|
|
400 |
pF |
(1)A Fast-mode I2C-bus device can be used in a Standard-mode I2C-bus system, but the requirement tsu(SDA-SCLH)³ 250 ns must then be met. This will automatically be the case if the device does not stretch the LOW period of the SCL signal. If such a device does stretch
the LOW period of the SCL signal, it must output the next data bit to the SDA line tr max + tsu(SDA-SCLH)= 1000 + 250 = 1250 ns (according to the Standard-mode I2C-Bus Specification) before the SCL line is released.
(2)A device must internally provide a hold time of at least 300 ns for the SDA signal (referred to the VIHmin of the SCL signal) to bridge the undefined region of the falling edge of SCL.
(3)The maximum th(SDA-SCLL) has only to be met if the 5502 I2C operates in master-receiver mode and the slave device does not stretch the LOW period [tw(SCLL)] of the SCL signal.
(4)Cb = total capacitance of one bus line in pF. If mixed with HS-mode devices, faster fall-times are allowed.
|
|
IC11 |
|
IC9 |
|
SDA |
|
|
|
|
|
IC8 |
IC6 |
IC14 |
|
|
|
IC4 |
IC13 |
|
|
IC10 |
IC5 |
|
|
|
|
||
|
SCL |
|
|
|
|
|
IC1 |
IC12 |
IC3 |
|
|
|
IC7 |
|
|
|
|
IC2 |
|
|
|
IC3 |
|
|
|
|
|
|
|
|
Stop |
Start |
Repeated |
Stop |
|
|
|
Start |
|
|
|
|
Figure 5-47. I2C Receive Timings |
|
180 |
Specifications |
|
|
Submit Documentation Feedback |
TMS320VC5502
Fixed-Point Digital Signal Processor
www.ti.com
SPRS166J –APRIL 2001 –REVISED AUGUST 2006
Table 5-49. I2C Signals (SDA and SCL) Switching Characteristics
NO.
IC16 
tc(SCL)
IC17 td(SCLH-SDAL)
IC18 td(SDAL-SCLL)
IC19 
tw(SCLL)
IC20 tw(SCLH)
IC21 
td(SDA-SCLH)
IC22 tv(SCLL-SDAV)
IC23 
tw(SDAH)
IC24 tr(SDA)
IC25 
tr(SCL)
IC26 tf(SDA)
IC27 
tf(SCL)
IC28 td(SCLH-SDAH)
IC29 
Cp
PARAMETER
Cycle time, SCL
Delay time, SCL high to SDA low for a repeated START condition
Delay time, SDA low to SCL low for a START and a repeated START condition
Pulse duration, SCL low
Pulse duration, SCL high
Delay time, SDA valid to SCL high
Valid time, SDA valid after SCL low
Pulse duration, SDA high between STOP and START conditions
Rise time, SDA
Rise time, SCL
Fall time, SDA
Fall time, SCL
Delay time, SCL high to SDA high for a STOP condition
Capacitance for each I2C pin
VC5502-200
VC5502-300
Standard |
Fast |
|
Mode |
Mode |
|
MIN MAX |
MIN |
|
10 |
|
2.5 |
4.7 |
|
0.6 |
4 |
|
0.6 |
4.7 |
|
1.3 |
4 |
|
0.6 |
250 |
100 |
|
0 |
|
0 |
4.7 |
|
1.3 |
1000 |
20 + 0.1C |
(1) |
|
|
b |
1000 |
20 + 0.1C |
(1) |
|
|
b |
300 |
20 + 0.1C |
(1) |
|
|
b |
300 |
20 + 0.1C |
(1) |
|
|
b |
4 |
|
0.6 |
10 |
|
|
(1)Cb = total capacitance of one bus line in pF. If mixed with HS-mode devices, faster fall-times are allowed.
|
UNIT |
MAX |
|
|
µs |
|
µs |
|
µs |
|
µs |
|
µs |
|
ns |
|
µs |
|
µs |
300 |
ns |
300 |
ns |
300 |
ns |
300 |
ns |
|
µs |
10 |
pF |
|
IC26 |
|
IC24 |
SDA |
|
|
|
|
IC23 |
IC21 |
|
|
|
IC19 |
IC28 |
|
IC25 |
IC20 |
|
|
|
||
SCL |
|
|
|
|
IC16 |
IC27 |
IC18 |
|
|
IC22 |
|
|
|
IC17 |
|
|
IC18 |
|
|
|
|
|
|
Stop |
Start |
Repeated |
Stop |
|
|
Start |
|
Figure 5-48. I2C Transmit Timings
Submit Documentation Feedback |
Specifications |
181 |
TMS320VC5502
Fixed-Point Digital Signal Processor
www.ti.com
SPRS166J –APRIL 2001 –REVISED AUGUST 2006
5.18 Universal Asynchronous Receiver/Transmitter (UART) Timings
Table 5-50 to Table 5-51 assume testing over recommended operating conditions (see Figure 5-49).
Table 5-50. UART Timing Requirements
|
|
|
|
VC5502-200 |
|
|
NO. |
|
|
|
VC5502-300 |
UNIT |
|
|
|
|
|
MIN |
MAX |
|
U4 |
t |
w(UDB)R |
Pulse width, receive data bit |
0.96U(1) |
1.05U(1) |
ns |
|
|
|
|
|
|
|
U5 |
t |
w(USB)R |
Pulse width, receive start bit |
0.96U(1) |
1.05U(1) |
ns |
(1)U = UART baud time = 1/programmed baud rate
Table 5-51. UART Switching Characteristics
|
|
|
VC5502-200 |
|
|
NO. |
|
PARAMETER |
VC5502-300 |
UNIT |
|
|
|
|
MIN |
MAX |
|
U1 |
fbaud |
Maximum programmable baud rate |
|
5 |
MHz |
U2 |
t |
Pulse width, transmit data bit |
U – 2(1) |
U + 2(1) |
ns |
|
w(UDB)X |
|
|
|
|
U3 |
t |
Pulse width, transmit start bit |
U – 2(1) |
U + 2(1) |
ns |
|
w(USB)X |
|
|
|
|
(1)U = UART baud time = 1/programmed baud rate
U3
Data Bits
|
Start |
UART.TX |
Bit |
U2
Data Bits
|
|
|
|
|
|
Start |
|
|
|||||
UART.RX |
|
|
|
|
|
Bit |
|
|
|
|
|
||
|
|
|
|
|
|
|
U4
U5
Figure 5-49. UART Timings
182 |
Specifications |
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