TMS320VC5502
Fixed-Point Digital Signal Processor
www.ti.com
SPRS166J –APRIL 2001 –REVISED AUGUST 2006
5.16 Host-Port Interface Timings
5.16.1HPI Read and Write Timings
Table 5-43 and Table 5-44 assume testing over recommended operating conditions (see Figure 5-39 through Figure 5-44).
Table 5-43. HPI Read and Write Timing Requirements(1) (2) (3)
NO.
H9 |
tsu(HASL-DSL) |
H10 |
th(DSL-HASL) |
H11 |
tsu(HAD-HASL) |
H12 |
th(HASL-HAD) |
H13 |
tw(DSL) |
H14 |
tw(DSH) |
H15 |
tsu(HAD-DSL) |
H16 |
th(DSL-HAD) |
H17 |
tsu(HD-DSH) |
H18 |
th(DSH-HD) |
H37 |
tsu(HCSL-DSL) |
H38 |
th(HRDYH-DSL) |
|
VC5502-200 |
|
|
VC5502-300 |
UNIT |
|
MIN |
MAX |
Setup time, HPI.HAS low before DS falling edge |
5 |
ns |
Hold time, HPI.HAS low after DS falling edge |
2 |
ns |
Setup time, HAD valid before HPI.HAS falling edge |
5 |
ns |
Hold time, HAD valid after HPI.HAS falling edge |
5 |
ns |
Pulse duration, DS low |
15 |
ns |
Pulse duration, DS high |
2P |
ns |
Setup time, HAD valid before DS falling edge |
5 |
ns |
Hold time, HAD valid after DS falling edge |
5 |
ns |
Setup time, HD valid before DS rising edge |
5 |
ns |
Hold time, HD valid after DS rising edge |
0 |
ns |
Setup time, HCS low before DS falling edge |
0 |
ns |
Hold time, DS low after HRDY rising edge |
0 |
ns |
(1)P = (Divider1 Ratio)/(CPU Clock Frequency) in ns. For example, when running parts at 300 MHz with the fast peripheral domain at 1/2 the CPU clock frequency, use P = 2/300 MHz = 6.66 ns.
(2)DS refers to logical OR of HCS, HDS1, and HDS2. HD refers to HPI Data Bus. HDS refers to HDS1 or HDS2. HAD refers to HCNTL0, HCNTL1, HPI.HBIL, and HR/W.
(3)A host must not initiate transfer requests until the HPI has been brought out of reset, see Section 3.8, Host-Port Interface (HPI), for more details.
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Fixed-Point Digital Signal Processor
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Table 5-44. HPI Read and Write Switching Characteristics(1) (2) (3)
NO.
H1 td(DSL-HDV)
H2 tdis(DSH-HDV)
H3 ten(DSL-HDD)
H4 td(DSL-HRDYL)
H5 td(DSH-HRDYL)
H6 td(DSL-HRDYH)
H7 td(HDV-HRDYH)
H8 td(COH-HINT)
H34 td(DSH-HRDYH)
H35 td(DSL-HRDYH)
H36 td(HASL-HRDYL)
PARAMETER
Delay time, DS low to HD valid
Case 1. HPIC or HPIA read
Case 2. HPID read with no auto-increment(4)
Case 3. HPID read with auto-increment and read FIFO initially empty(4)
|
VC5502-200 |
|
|
|
VC5502-300 |
UNIT |
|
MIN |
|
MAX |
|
5 |
|
15 |
|
K = 1(5) |
9 |
* 2H + 20 |
|
K = 2(5) |
10 |
* 2H + 20 |
|
K = 4(5) |
11 |
* 2H + 20 |
|
K = 1(5) |
9 |
* 2H + 20 |
ns |
K = 2(5) |
10 |
* 2H + 20 |
|
K = 4(5) |
11 |
* 2H + 20 |
|
Case 4. HPID read with auto-increment and data previously prefetched into the read FIFO
Disable time, HD high-impedance from DS high
Enable time, HD driven from DS low
Delay time, DS low to HRDY low
Delay time, DS high to HRDY low
Case 1. HPID read with no auto-increment(4)
Delay time, DS low to HRDY
high
Case 2. HPID read with auto-increment and read FIFO initialy empty(4)
Delay time, HD valid to HRDY high
Delay time, CLKOUT high to HINT change(6)
Case 1. HPIA write(4)
Delay time, DS high to HRDY
high Case 2. HPID write with no auto-increment(4)
Delay time, DS low to HRDY high for HPIA write and FIFO not empty(4)
Delay time, HPI.HAS low to HRDY low
K = 1(5)
K = 2(5)
K = 4(5)
K = 1(5)
K = 2(5)
K = 4(5)
K = 1, 2, 4(5)
K = 1(5)
K = 2(5)
K = 4(5)
K = 1(5)
K = 2(5)
K = 4(5)
5 |
15 |
|
|
1 |
4 |
ns |
|
3 |
15 |
ns |
|
|
12 |
ns |
|
|
12 |
ns |
|
10 |
* 2H + 20 |
|
|
11 |
* 2H + 20 |
|
|
12 |
* 2H + 20 |
ns |
|
10 |
* 2H + 20 |
||
|
|||
11 |
* 2H + 20 |
|
|
12 |
* 2H + 20 |
|
|
0 |
|
ns |
|
|
8 |
ns |
|
5 |
* 2H + 20 |
|
|
5 |
* 2H + 20 |
ns |
|
5 |
* 2H + 20 |
||
|
|||
6 |
* 2H + 20 |
|
|
40 |
* 2H + 20 |
|
|
40 |
* 2H + 20 |
ns |
|
24 |
* 2H + 20 |
|
|
|
12 |
ns |
(1)DS refers to logical OR of HCS, HDS1, and HDS2. HD refers to HPI Data Bus. HDS refers to HDS1 or HDS2. HAD refers to HCNTL0,
HCNTL1, HPI.HBIL, and HR/W.
(2)H is half the SYSCLK1 clock cycle.
(3)A host must not initiate transfer requests until the HPI has been brought out of reset, see Section 3.8, Host-Port Interface (HPI), for more details.
(4)Assumes no other DMA or CPU memory activity.
(5)K = divider ratio between CPU clock and SYSCLK1. For example, when SYSCLK1 is set to the CPU clock divided by four, use K = 4.
(6)In this case, CLKOUT reflects SYSCLK1. The CLKOUT Selection Register (CLKOUTSR) can be programmed to select SYSCLK1 as CLKOUT.
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Fixed-Point Digital Signal Processor
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SPRS166J –APRIL 2001 –REVISED AUGUST 2006 |
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Read |
Write |
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HCS |
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H37 |
H37 |
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H14 |
||
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||
H13 |
H13 |
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HDSx |
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H15 |
H15 |
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H16 |
H16 |
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HR/W |
|
HPI.HA[15:0] |
Valid |
|
Valid |
|
H1 |
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H3 |
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H2 |
HPI.HD[15:0] |
|
Read data |
|
(Read) |
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H18 |
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H17 |
HPI.HD[15:0] |
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Write data |
(Write) |
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H4 |
H7 |
H34 |
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H6 |
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H5 |
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HRDY |
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|
(A ) Depending on the type of write or read operation (HPID or HPIC), transitions on HRDY may or may not occur [see the TMS320VC5501/5502 DSP Host Port Interface (HPI) Reference Guide (literature number SPRU620)].
Figure 5-39. Non-Multiplexed Read/Write Timings
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Fixed-Point Digital Signal Processor
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SPRS166J –APRIL 2001 –REVISED AUGUST 2006
HCS |
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HPI.HAS |
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H12 |
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H11 |
H12 |
H11 |
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||
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||
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HCNTL[1:0] |
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H12 |
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H12 |
H11 |
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H11 |
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HR/W |
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H12 |
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H12 |
H11 |
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H11 |
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HPI.HBIL |
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H10 |
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H10 |
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H9 |
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H9 |
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H37 |
H13 |
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H37 |
H13 |
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H14 |
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||
DS |
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H1 |
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H1 |
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H3 |
H2 |
H3 |
H2 |
HPI.HD[7:0] |
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H7 |
H38 |
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H36 |
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H6 |
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HRDY
(A ) Depending on the type of write or read operation (HPID without auto-incrementing, HPIA, HPIC, or HPID with auto-incrementing) and the state of the FIFO, transitions on HRDY may or may not occur [see the TMS320VC5501/5502 DSP Host Port Interface (HPI) Reference Guide (literature number SPRU620)].
Figure 5-40. Multiplexed Read Timings Using HPI.HAS
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TMS320VC5502
Fixed-Point Digital Signal Processor
www.ti.com
SPRS166J –APRIL 2001 –REVISED AUGUST 2006
HCS
HPI.HAS |
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HCNTL[1:0] |
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HR/W |
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HPI.HBIL |
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H13 |
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H16 |
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H16 |
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H15 |
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H15 |
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H37 |
H13 |
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H37 |
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H14 |
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||
DS |
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H3 |
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H3 |
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H1 |
H2 |
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H1 |
H2 |
HPI.HD[7:0] |
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H38 |
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H4 |
H7 |
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H6 |
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HRDY |
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(A ) Depending on the type of write or read operation (HPID without auto-incrementing, HPIA, HPIC, or HPID with auto-incrementing) and the state of the FIFO, transitions on HRDY may or may not occur [see the TMS320VC5501/5502 DSP Host Port Interface (HPI) Reference Guide (literature number SPRU620)].
Figure 5-41. Multiplexed Read Timings With HPI.HAS Held High
174 |
Specifications |
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TMS320VC5502 |
www.ti.com |
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Fixed-Point Digital Signal Processor |
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SPRS166J –APRIL 2001 –REVISED AUGUST 2006 |
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HCS |
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HPI.HAS |
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H12 |
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H12 |
H11 |
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H11 |
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HCNTL[1:0] |
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H12 |
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H12 |
H11 |
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H11 |
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HR/W |
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H12 |
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H12 |
H11 |
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H11 |
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HPI.HBIL |
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H10 |
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H9 |
H9 |
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H10 |
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H37 |
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H37 |
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H14 |
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DS |
H13 |
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H13 |
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H18 |
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H18 |
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H17 |
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H17 |
HPI.HD[7:0] |
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H35 |
H34 |
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H5 |
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H34 |
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H36 |
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H38 |
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H5 |
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HRDY
(A ) Depending on the type of write or read operation (HPID without auto-incrementing, HPIA, HPIC, or HPID with auto-incrementing) and the state of the FIFO, transitions on HRDY may or may not occur [see the TMS320VC5501/5502 DSP Host Port Interface (HPI) Reference Guide (literature number SPRU620)].
Figure 5-42. Multiplexed Write Timings Using HPI.HAS
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TMS320VC5502
Fixed-Point Digital Signal Processor
www.ti.com
SPRS166J –APRIL 2001 –REVISED AUGUST 2006
HCS
HPI.HAS |
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HCNTL[1:0] |
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|
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HR/W |
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|
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HPI.HBIL |
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H16 |
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H16 |
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H13 |
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H15 |
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H15 |
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H37 |
H13 |
H37 |
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H14 |
|
DS |
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H18 |
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H18 |
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H17 |
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H17 |
HPI.HD[7:0] |
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H38 |
H34 |
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H4 |
H5 |
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H34 |
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|||
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H35 |
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|
H5 |
HRDY
(A ) Depending on the type of write or read operation (HPID without auto-incrementing, HPIA, HPIC, or HPID with auto-incrementing) and the state of the FIFO, transitions on HRDY may or may not occur [see the TMS320VC5501/5502 DSP Host Port Interface (HPI) Reference Guide (literature number SPRU620)].
Figure 5-43. Multiplexed Write Timings With HPI.HAS Held High
CLKOUT
H8
HINT
Figure 5-44. HINT Timings
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Specifications |
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Fixed-Point Digital Signal Processor
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SPRS166J –APRIL 2001 –REVISED AUGUST 2006
5.16.2HPI General-Purpose I/O Timings
Table 5-45 and Table 5-46 assume testing over recommended operating conditions (see Figure 5-45).
Table 5-45. HPI General-Purpose I/O Timing Requirements(1)
NO.
H23 tsu(HAGPIO-COH)
H24 th(COH-HAGPIO)
H25 tsu(HDNMGPIO-COH)
H26 th(COH-HDNMGPIO)
H27 tsu(HDMGPIO-COH)
H28 th(COH-HDMGPIO)
H29 tsu(HCGPIO-COH)
H30 th(COH-HCGPIO)
|
VC5502-200 |
|
|
VC5502-300 |
UNIT |
|
MIN MAX |
|
Setup time, HAGPIO input mode before CLKOUT high(2) |
5 |
ns |
Hold time, HAGPIO input mode after CLKOUT high(2) |
0 |
ns |
Setup time, HDNMGPIO input mode before CLKOUT high(3) |
5 |
ns |
Hold time, HDNMGPIO input mode after CLKOUT high(3) |
0 |
ns |
Setup time, HDMGPIO input mode before CLKOUT high(4) |
5 |
ns |
Hold time, HDMGPIO input mode after CLKOUT high(4) |
0 |
ns |
Setup time, HCGPIO input mode before CLKOUT high(5) |
5 |
ns |
Hold time, HCGPIO input mode after CLKOUT high(5) |
0 |
ns |
(1)In this case, CLKOUT reflects SYSCLK1. The CLKOUT Selection Register (CLKOUTSR) can be programmed to select SYSCLK1 as CLKOUT.
(2)HAGPIO refers to HPI.HA[15:0] configured as general-purpose input.
(3)HDNMGPIO refers to HPI.HD[15:0] configured as general-purpose input during non-multiplexed operation of the HPI.
(4)HDMGPIO refers to HPI.HD[7:0] configured as general-purpose input during multiplexed operation of the HPI.
(5)HCGPIO refers to HPI.HAS (multiplexed mode only), HPI.HBIL (multiplexed mode only), HCNTL0, HCNTL1, HCS, HR/W, HDS1, HDS2, HRDY, and HINT configured as general-purpose input.
Table 5-46. HPI General-Purpose I/O Switching Characteristics(1)
NO.
H19 td(COH-HAGPIO)
H20 td(COH-HDNMGPIO)
H21 td(COH-HDMGPIO)
H22 td(COH-HCGPIO)
|
VC5502-200 |
|
PARAMETER |
VC5502-300 |
UNIT |
|
MIN MAX |
|
Delay time, CLKOUT high to HAGPIO output mode(2) |
10 |
ns |
Delay time, CLKOUT high to HDNMGPIO output mode(3) |
10 |
ns |
Delay time, CLKOUT high to HDMGPIO output mode(4) |
10 |
ns |
Delay time, CLKOUT high to HCGPIO output mode(5) |
10 |
ns |
(1)In this case, CLKOUT reflects SYSCLK1. The CLKOUT Selection Register (CLKOUTSR) can be programmed to select SYSCLK1 as CLKOUT.
(2)HAGPIO refers to HPI.HA[15:0] configured as general-purpose output.
(3)HDNMGPIO refers to HPI.HD[15:0] configured as general-purpose output during non-multiplexed operation of the HPI.
(4)HDMGPIO refers to HPI.HD[7:0] configured as general-purpose output during multiplexed operation of the HPI.
(5)HCGPIO refers to HPI.HAS (multiplexed mode only), HPI.HBIL (multiplexed mode only), HCNTL0, HCNTL1, HCS, HR/W, HDS1, HDS2, HRDY, and HINT configured as general-purpose output.
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TMS320VC5502
Fixed-Point Digital Signal Processor
www.ti.com
SPRS166J –APRIL 2001 –REVISED AUGUST 2006
CLKOUT
H23
H24
HAGPIO
Input Mode
H19
HAGPIO
Output Mode
H25
H26
HDNMGPIO
Input Mode
H20
HDNMGPIO
Output Mode
H27
H28
HDMGPIO
Input Mode
H21
HDMGPIO
Output Mode
H29
H30
HCGPIO
Input Mode
H22
HCGPIO
Output Mode
Figure 5-45. HPI General-Purpose I/O Timings
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