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Аналіз обчислювальної похибки при виконанні базових операцій алгоритмів цифрової обробки сигналів. Обчислення математичних функцій роектування комп’ютерних засобів обробки сигналів та зображень Ваврук. Лаби для 13 групи / MAZ / MAZ-DOD-MAT-2012 / tms320vc5502.pdf

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TMS320VC5502

Fixed-Point Digital Signal Processor

www.ti.com

SPRS166J –APRIL 2001 –REVISED AUGUST 2006

5.15.3 McBSP as SPI Master or Slave Timings

Table 5-35 to Table 5-42 assume testing over recommended operating conditions (see Figure 5-35 through Figure 5-38).

Table 5-35. McBSP as SPI Master or Slave Timing Requirements (CLKSTP = 10b, CLKXP = 0)(1) (2) (3)

NO.

M30 tsu(DRV-CKXL)

M31 th(CKXL-DRV)

M32 tsu(FXL-CKXH)

M33 tc(CKX)

		VC5502-200
		VC5502-300		UNIT
	MASTER		SLAVE	UNIT
	MASTER		SLAVE
	MIN	MAX	MIN	MAX
Setup time, DR valid before CLKX low	13		0 – 5P	ns
Hold time, DR valid after CLKX low	1		9 + 6P	ns
Setup time, FSX low before CLKX high			10	ns
Cycle time, CLKX	2P		16P	ns

(1)For all SPI slave modes, CLKG is programmed as 1/2 of the CPU clock by setting CLKSM = CLKGDV = 1.

(2)P = (Divider2 Ratio)/(CPU Clock Frequency) in ns. For example, when running parts at 300 MHz with the slow peripheral domain at 1/2 the CPU clock frequency, use P = 2/300 MHz = 6.66 ns.

(3)McBSP register values required to configure the McBSP as an SPI master and as an SPI slave are listed in the

TMS320VC5501/5502/5503/5507/5509/5510 DSP Multichannel Buffered Serial Port (McBSP) Reference Guide (literature number SPRU592).

Table 5-36. McBSP as SPI Master or Slave Switching Characteristics (CLKSTP = 10b, CLKXP = 0)(1) (2) (3) (4)

NO.

PARAMETER

M24 td(CKXL-FXL)

M25 td(FXL-CKXH)

M26 td(CKXH-DXV)

M27 tdis(CKXL-DXHZ)

M28 tdis(FXH-DXHZ)

M29 td(FXL-DXV)

Delay time, CLKX low to FSX low(5)

Delay time, FSX low to CLKX high(6)

Delay time, CLKX high to DX valid

Disable time, DX high impedance following last data bit from CLKX low

Disable time, DX high impedance following last data bit from FSX high

Delay time, FSX low to DX valid

	VC5502-200
	VC5502-300			UNIT
MASTER		SLAVE		UNIT
MASTER		SLAVE
MIN	MAX	MIN	MAX
T – 2	T + 6			ns
C – 6	C + 4			ns
–4	6	4P	6P	ns
C – 2	C +10			ns
		2P + 4	4P + 10	ns
		2P + 4	4P + 10	ns

(1)For all SPI slave modes, CLKG is programmed as 1/2 of the CPU clock by setting CLKSM = CLKGDV = 1.

(2)P = (Divider2 Ratio)/(CPU Clock Frequency) in ns. For example, when running parts at 300 MHz with the slow peripheral domain at 1/2 the CPU clock frequency, use P = 2/300 MHz = 6.66 ns.

(3)McBSP register values required to configure the McBSP as an SPI master and as an SPI slave are listed in the

TMS320VC5501/5502/5503/5507/5509/5510 DSP Multichannel Buffered Serial Port (McBSP) Reference Guide (literature number SPRU592).

(4)T = BCLKX period = (1 + CLKGDV) * 2P

C = BCLKX low pulse width = T/2 when CLKGDV is odd or zero and = (CLKGDV/2) * 2P when CLKGDV is even

(5)FSRP = FSXP = 1. As a SPI master, FSX is inverted to provide active-low slave-enable output. As a slave, the active-low signal input on FSX and FSR is inverted before being used internally.

CLKXM = FSXM = 1, CLKRM = FSRM = 0 for master McBSP CLKXM = CLKRM = FSXM = FSRM = 0 for slave McBSP

(6)FSX should be low before the rising edge of clock to enable slave devices and then begin a SPI transfer at the rising edge of the master clock (CLKX).

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Specifications

163

TMS320VC5502

Fixed-Point Digital Signal Processor

www.ti.com

SPRS166J –APRIL 2001 –REVISED AUGUST 2006
	LSB	M32	MSB		M33
CLKX
		M25
	M24			M26
	M24
FSX
	M28
	M27	M29
	M27
DX	Bit 0		Bit (n-1)	(n-2)	(n-3)	(n-4)
		M30		M31
				M31
DR	Bit 0		Bit (n-1)	(n-2)	(n-3)	(n-4)

Figure 5-35. McBSP Timings as SPI Master or Slave: CLKSTP = 10b, CLKXP = 0

164

Specifications

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TMS320VC5502

Fixed-Point Digital Signal Processor

www.ti.com

SPRS166J –APRIL 2001 –REVISED AUGUST 2006

Table 5-37. McBSP as SPI Master or Slave Timing Requirements (CLKSTP = 11b, CLKXP = 0)(1) (2) (3)

NO.

M39 tsu(DRV-CKXH)

M40 th(CKXH-DRV)

M41 tsu(FXL-CKXH)

M42 tc(CKX)

		VC5502-200
		VC5502-300		UNIT
	MASTER		SLAVE	UNIT
	MASTER		SLAVE
	MIN	MAX	MIN	MAX
Setup time, DR valid before CLKX high	13		0 – 5P	ns
Hold time, DR valid after CLKX high	1		9 + 6P	ns
Setup time, FSX low before CLKX high			10	ns
Cycle time, CLKX	2P		16P	ns

(1)For all SPI slave modes, CLKG is programmed as 1/2 of the CPU clock by setting CLKSM = CLKGDV = 1.

(2)P = (Divider2 Ratio)/(CPU Clock Frequency) in ns. For example, when running parts at 300 MHz with the slow peripheral domain at 1/2 the CPU clock frequency, use P = 2/300 MHz = 6.66 ns.

(3)McBSP register values required to configure the McBSP as an SPI master and as an SPI slave are listed in the

TMS320VC5501/5502/5503/5507/5509/5510 DSP Multichannel Buffered Serial Port (McBSP) Reference Guide (literature number SPRU592).

Table 5-38. McBSP as SPI Master or Slave Switching Characteristics (CLKSTP = 11b, CLKXP = 0)(1) (2) (3) (4)

NO.

M34 td(CKXL-FXL)

M35 td(FXL-CKXH)

M36 td(CKXL-DXV)

M37 tdis(CKXL-DXHZ)

M38 td(FXL-DXV)

		VC5502-200
PARAMETER		VC5502-300		UNIT
PARAMETER	MASTER		SLAVE	UNIT
	MASTER		SLAVE
	MIN	MAX	MIN	MAX

Delay time, CLKX low to FSX low(5)

Delay time, FSX low to CLKX high(6)

Delay time, CLKX low to DX valid

Disable time, DX high impedance following last data bit from CLKX low

Delay time, FSX low to DX valid

C – 2	C + 6			ns
T – 6	T + 4			ns
–4	6	4P	6P	ns
–2	10	3P + 4	4P + 18	ns
D – 2	D + 10	2P – 4	4P + 10	ns

(1)For all SPI slave modes, CLKG is programmed as 1/2 of the CPU clock by setting CLKSM = CLKGDV = 1.

(2)P = (Divider2 Ratio)/(CPU Clock Frequency) in ns. For example, when running parts at 300 MHz with the slow peripheral domain at 1/2 the CPU clock frequency, use P = 2/300 MHz = 6.66 ns.

(3)McBSP register values required to configure the McBSP as an SPI master and as an SPI slave are listed in the

TMS320VC5501/5502/5503/5507/5509/5510 DSP Multichannel Buffered Serial Port (McBSP) Reference Guide (literature number SPRU592).

(4)T = CLKX period = (1 + CLKGDV) * P

C = CLKX low pulse width = T/2 when CLKGDV is odd or zero and = (CLKGDV/2) * P when CLKGDV is even

D = CLKX high pulse width = T/2 when CLKGDV is odd or zero and = (CLKGDV/2 + 1) * P when CLKGDV is even

(5)FSRP = FSXP = 1. As a SPI master, FSX is inverted to provide active-low slave-enable output. As a slave, the active-low signal input on FSX and FSR is inverted before being used internally.

CLKXM = FSXM = 1, CLKRM = FSRM = 0 for master McBSP CLKXM = CLKRM = FSXM = FSRM = 0 for slave McBSP

(6)FSX should be low before the rising edge of clock to enable slave devices and then begin a SPI transfer at the rising edge of the master clock (CLKX).

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Specifications

165

TMS320VC5502

Fixed-Point Digital Signal Processor

www.ti.com

SPRS166J –APRIL 2001 –REVISED AUGUST 2006
	LSB	M41	MSB		M42
	LSB		MSB
CLKX
		M35
	M34			M36
FSX
	M37		M38
	M37
DX	Bit 0		Bit (n-1)	(n-2)	(n-3)	(n-4)
		M39		M40
				M40
DR	Bit 0		Bit (n-1)	(n-2)	(n-3)	(n-4)

Figure 5-36. McBSP Timings as SPI Master or Slave: CLKSTP = 11b, CLKXP = 0

Table 5-39. McBSP as SPI Master or Slave Timing Requirements (CLKSTP = 10b, CLKXP = 1)(1) (2) (3)

NO.

M49 tsu(DRV-CKXH)

M50 th(CKXH-DRV)

M51 tsu(FXL-CKXL)

M52 tc(CKX)

		VC5502-200
		VC5502-300		UNIT
	MASTER		SLAVE	UNIT
	MASTER		SLAVE
	MIN	MAX	MIN	MAX
Setup time, DR valid before CLKX high	13		0 – 5P	ns
Hold time, DR valid after CLKX high	1		9 + 6P	ns
Setup time, FSX low before CLKX low			10	ns
Cycle time, CLKX	2P		16P	ns

(1)For all SPI slave modes, CLKG is programmed as 1/2 of the CPU clock by setting CLKSM = CLKGDV = 1.

(2)P = (Divider2 Ratio)/(CPU Clock Frequency) in ns. For example, when running parts at 300 MHz with the slow peripheral domain at 1/2 the CPU clock frequency, use P = 2/300 MHz = 6.66 ns.

(3)McBSP register values required to configure the McBSP as an SPI master and as an SPI slave are listed in the

TMS320VC5501/5502/5503/5507/5509/5510 DSP Multichannel Buffered Serial Port (McBSP) Reference Guide (literature number SPRU592).

Table 5-40. McBSP as SPI Master or Slave Switching Characteristics (CLKSTP = 10b, CLKXP = 1)(1) (2) (3) (4)

NO.

M43 td(CKXH-FXL)

M44 td(FXL-CKXL)

M45 td(CKXL-DXV)

		VC5502-200
PARAMETER		VC5502-300			UNIT
PARAMETER	MASTER		SLAVE		UNIT
	MASTER		SLAVE
	MIN	MAX	MIN	MAX
Delay time, CLKX high to FSX low(5)	T – 2	T + 6			ns
Delay time, FSX low to CLKX low(6)	D – 6	D + 4			ns
Delay time, CLKX low to DX valid	–4	6	4P	6P	ns

(1)For all SPI slave modes, CLKG is programmed as 1/2 of the CPU clock by setting CLKSM = CLKGDV = 1.

(2)P = (Divider2 Ratio)/(CPU Clock Frequency) in ns. For example, when running parts at 300 MHz with the slow peripheral domain at 1/2 the CPU clock frequency, use P = 2/300 MHz = 6.66 ns.

(3)McBSP register values required to configure the McBSP as an SPI master and as an SPI slave are listed in the

TMS320VC5501/5502/5503/5507/5509/5510 DSP Multichannel Buffered Serial Port (McBSP) Reference Guide (literature number SPRU592).

(4)T = CLKX period = (1 + CLKGDV) * P

D = CLKX high pulse width = T/2 when CLKGDV is odd or zero and = (CLKGDV/2 + 1) * P when CLKGDV is even

(5)FSRP = FSXP = 1. As a SPI master, FSX is inverted to provide active-low slave-enable output. As a slave, the active-low signal input on FSX and FSR is inverted before being used internally.

CLKXM = FSXM = 1, CLKRM = FSRM = 0 for master McBSP CLKXM = CLKRM = FSXM = FSRM = 0 for slave McBSP

(6)FSX should be low before the rising edge of clock to enable slave devices and then begin a SPI transfer at the rising edge of the master clock (CLKX).

166

Specifications

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TMS320VC5502

Fixed-Point Digital Signal Processor

www.ti.com

SPRS166J –APRIL 2001 –REVISED AUGUST 2006

Table 5-40. McBSP as SPI Master or Slave Switching Characteristics (CLKSTP = 10b, CLKXP = 1) (continued)

NO.

M46 tdis(CKXH-DXHZ)

M47 tdis(FXH-DXHZ)

M48 td(FXL-DXV)

PARAMETER

Disable time, DX high impedance following last data bit from CLKX high

Disable time, DX high impedance following last data bit from FSX high

Delay time, FSX low to DX valid

	VC5502-200
	VC5502-300			UNIT
MASTER		SLAVE		UNIT
MASTER		SLAVE
MIN	MAX	MIN	MAX
D – 2	D + 10			ns
		2P + 4	4P + 10	ns
		2P – 4	4P + 10	ns

	LSB	M51			M52
	LSB	MSB			M52
CLKX
		M44
	M43		M45
FSX
		M47
		M48
		M46
DX	Bit 0	Bit (n-1)	(n-2)	(n-3)	(n-4)
		M49	M50
			M50
DR	Bit 0	Bit (n-1)	(n-2)	(n-3)	(n-4)

Figure 5-37. McBSP Timings as SPI Master or Slave: CLKSTP = 10b, CLKXP = 1

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Specifications

167

TMS320VC5502

Fixed-Point Digital Signal Processor

www.ti.com

SPRS166J –APRIL 2001 –REVISED AUGUST 2006

Table 5-41. McBSP as SPI Master or Slave Timing Requirements (CLKSTP = 11b, CLKXP = 1)(1) (2) (3)

NO.

M58 tsu(DRV-CKXL)

M59 th(CKXL-DRV)

M60 tsu(FXL-CKXL)

M61 tc(CKX)

		VC5502-200
		VC5502-300		UNIT
	MASTER		SLAVE	UNIT
	MASTER		SLAVE
	MIN	MAX	MIN	MAX
Setup time, DR valid before CLKX low	13		0 – 5P	ns
Hold time, DR valid after CLKX low	1		9 + 6P	ns
Setup time, FSX low before CLKX low			10	ns
Cycle time, CLKX	2P		16P	ns

(1)For all SPI slave modes, CLKG is programmed as 1/2 of the CPU clock by setting CLKSM = CLKGDV = 1.

(2)P = (Divider2 Ratio)/(CPU Clock Frequency) in ns. For example, when running parts at 300 MHz with the slow peripheral domain at 1/2 the CPU clock frequency, use P = 2/300 MHz = 6.66 ns.

(3)McBSP register values required to configure the McBSP as an SPI master and as an SPI slave are listed in the

TMS320VC5501/5502/5503/5507/5509/5510 DSP Multichannel Buffered Serial Port (McBSP) Reference Guide (literature number SPRU592).

Table 5-42. McBSP as SPI Master or Slave Switching Characteristics (CLKSTP = 11b, CLKXP = 1)(1) (2) (3) (4)

NO.

M53 td(CKXH-FXL)

M54 td(FXL-CKXL)

M55 td(CKXH-DXV)

M56 tdis(CKXH-DXHZ)

M57 td(FXL-DXV)

		VC5502-200
PARAMETER		VC5502-300		UNIT
PARAMETER	MASTER		SLAVE	UNIT
	MASTER		SLAVE
	MIN	MAX	MIN	MAX

Delay time, CLKX high to FSX low(5)

Delay time, FSX low to CLKX low(6)

Delay time, CLKX high to DX valid

Disable time, DX high impedance following last data bit from CLKX high

Delay time, FSX low to DX valid

D – 2	D + 6			ns
T – 6	T + 4			ns
–4	6	4P	6P	ns
–2	10	3P + 4	4P + 18	ns
C – 2	C + 10	2P – 4	4P + 10	ns

(1)For all SPI slave modes, CLKG is programmed as 1/2 of the CPU clock by setting CLKSM = CLKGDV = 1.

(2)P = (Divider2 Ratio)/(CPU Clock Frequency) in ns. For example, when running parts at 300 MHz with the slow peripheral domain at 1/2 the CPU clock frequency, use P = 2/300 MHz = 6.66 ns.

(3)McBSP register values required to configure the McBSP as an SPI master and as an SPI slave are listed in the

TMS320VC5501/5502/5503/5507/5509/5510 DSP Multichannel Buffered Serial Port (McBSP) Reference Guide (literature number SPRU592).

(4)T = CLKX period = (1 + CLKGDV) * P

C = CLKX low pulse width = T/2 when CLKGDV is odd or zero and = (CLKGDV/2) * P when CLKGDV is even

D = CLKX high pulse width = T/2 when CLKGDV is odd or zero and = (CLKGDV/2 + 1) * P when CLKGDV is even

(5)FSRP = FSXP = 1. As a SPI master, FSX is inverted to provide active-low slave-enable output. As a slave, the active-low signal input on FSX and FSR is inverted before being used internally.

CLKXM = FSXM = 1, CLKRM = FSRM = 0 for master McBSP CLKXM = CLKRM = FSXM = FSRM = 0 for slave McBSP

(6)FSX should be low before the rising edge of clock to enable slave devices and then begin a SPI transfer at the rising edge of the master clock (CLKX).

168

Specifications

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					TMS320VC5502
www.ti.com			Fixed-Point Digital Signal Processor
www.ti.com				SPRS166J –APRIL 2001 –REVISED AUGUST 2006
				SPRS166J –APRIL 2001 –REVISED AUGUST 2006
	LSB	M60		M61
	LSB	MSB		M61
CLKX
		M54
	M53		M55
FSX
	M56	M57
	M56
DX	Bit 0	Bit (n-1)	(n-2)	(n-3)	(n-4)
		M58	M59
			M59
DR	Bit 0	Bit (n-1)	(n-2)	(n-3)	(n-4)

Figure 5-38. McBSP Timings as SPI Master or Slave: CLKSTP = 11b, CLKXP = 1

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Specifications

169

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