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Аналіз обчислювальної похибки при виконанні базових операцій алгоритмів цифрової обробки сигналів. Обчислення математичних функцій роектування комп’ютерних засобів обробки сигналів та зображень Ваврук. Лаби для 13 групи / MAZ / MAZ-DOD-MAT-2012 / tms320vc5502.pdf

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TMS320VC5502

Fixed-Point Digital Signal Processor

www.ti.com

SPRS166J –APRIL 2001 –REVISED AUGUST 2006

5.15 Multichannel Buffered Serial Port (McBSP) Timings

5.15.1McBSP Transmit and Receive Timings

Table 5-31 and Table 5-32 assume testing over recommended operating conditions (see Figure 5-32 and Figure 5-33).

Table 5-31. McBSP Transmit and Receive Timing Requirements(1) (2)

NO.

M11 tc(CKRX)

M12 tw(CKRX)

M13 tr(CKRX)

M14 tf(CKRX)

M15 tsu(FRH-CKRL)

M16 th(CKRL-FRH)

M17 tsu(DRV-CKRL)

M18 th(CKRL-DRV)

M19 tsu(FXH-CKXL)

M20 th(CKXL-FXH)

		VC5502-200
		VC5502-300	UNIT
		MIN MAX
Cycle time, CLKR/X	CLKR/X ext	2P	ns
Pulse duration, CLKR/X high or CLKR/X low	CLKR/X ext	P – 2	ns
Rise time, CLKR/X	CLKR/X ext	5	ns
Fall time, CLKR/X	CLKR/X ext	5	ns
Setup time, external FSR high before CLKR low	CLKR int	5	ns
Setup time, external FSR high before CLKR low	CLKR ext	1	ns
	CLKR ext	1
Hold time, external FSR high after CLKR low	CLKR int	1	ns
Hold time, external FSR high after CLKR low	CLKR ext	6	ns
	CLKR ext	6
Setup time, DR valid before CLKR low	CLKR int	3	ns
Setup time, DR valid before CLKR low	CLKR ext	1	ns
	CLKR ext	1
Hold time, DR valid after CLKR low	CLKR int	1	ns
Hold time, DR valid after CLKR low	CLKR ext	6	ns
	CLKR ext	6
Setup time, external FSX high before CLKX low	CLKX int	5	ns
Setup time, external FSX high before CLKX low	CLKX ext	1	ns
	CLKX ext	1
Hold time, external FSX high after CLKX low	CLKX int	1	ns
Hold time, external FSX high after CLKX low	CLKX ext	6	ns
	CLKX ext	6

(1)Polarity bits CLKRP = CLKXP = FSRP = FSXP = 0. If the polarity of any of the signals is inverted, then the timing references of that signal are also inverted.

(2)P = (Divider2 Ratio)/(CPU Clock Frequency) in ns. For example, when running parts at 300 MHz with the slow peripheral domain at 1/2 the CPU clock frequency, use P = 2/300 MHz = 6.66 ns.

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159

TMS320VC5502

Fixed-Point Digital Signal Processor

www.ti.com

SPRS166J –APRIL 2001 –REVISED AUGUST 2006

Table 5-32. McBSP Transmit and Receive Switching Characteristics(1) (2)

NO.

M1	tc(CKRX)
M2	tw(CKRXH)
M3	tw(CKRXL)
M4	td(CKRH-FRV)
M5	td(CKXH-FXV)
M6	tdis(CKXH-DXHZ)

M7 td(CKXH-DXV)

M8 ten(CKXH-DX)

M9 td(FXH-DXV)

M10 ten(FXH-DX)

PARAMETER

Cycle time, CLKR/X

Pulse duration, CLKR/X high

Pulse duration, CLKR/X low

Delay time, CLKR high to internal FSR valid

Delay time, CLKX high to internal FSX valid

Disable time, CLKX high to DX high impedance following last data bit

Delay time, CLKX high to DX valid.

This applies to all bits except the first bit transmitted.

Delay time, CLKX high to DX valid(4) Only applies to first bit transmitted when in Data Delay 1 or 2 (XDATDLY=01b or 10b) modes

Enable time, CLKX high to DX driven(4) Only applies to first bit transmitted when in Data Delay 1 or 2 (XDATDLY=01b or 10b) modes

Delay time, FSX high to DX valid(4) Only applies to first bit transmitted when in Data Delay 0 (XDATDLY=00b) mode.

Enable time, FSX high to DX driven(4) Only applies to first bit transmitted when in Data Delay 0 (XDATDLY=00b) mode

DXENA = 0

DXENA = 1

DXENA = 0

DXENA = 1

DXENA = 0

DXENA = 1

DXENA = 0

DXENA = 1

	VC5502-200
	VC5502-300		UNIT
	MIN	MAX
CLKR/X int	2P		ns
CLKR/X int	D – 1(3)	D + 1(3)	ns
CLKR/X int	C – 1(3)	C + 1(3)	ns
CLKR int	–2	6	ns
CLKR ext	4	16	ns
CLKR ext	4	16
CLKX int	0	6	ns
CLKX ext	4	16	ns
CLKX ext	4	16
CLKX int	–5	5	ns
CLKX ext	1	11	ns
CLKX ext	1	11
CLKX int		6
CLKX ext		16
CLKX int		6	ns
CLKX ext		16	ns
CLKX ext		16
CLKX int		2P + 2
CLKX ext		2P + 8
CLKX int	0
CLKX ext	6		ns
CLKX int	2P		ns
CLKX int	2P
CLKX ext	2P + 6
FSX int		2
FSX ext		7	ns
FSX int		2P + 2	ns
FSX int		2P + 2
FSX ext		2P + 7
FSX int	0
FSX ext	6		ns
FSX int	2P		ns
FSX int	2P
FSX ext	P + 6

(1)Polarity bits CLKRP = CLKXP = FSRP = FSXP = 0. If the polarity of any of the signals is inverted, then the timing references of that signal are also inverted.

(2)P = (Divider2 Ratio)/(CPU Clock Frequency) in ns. For example, when running parts at 300 MHz with the slow peripheral domain at 1/2 the CPU clock frequency, use P = 2/300 MHz = 6.66 ns.

(3)T = CLKRX period = (1 + CLKGDV) * P

C = CLKRX low pulse width = T/2 when CLKGDV is odd or zero and = (CLKGDV/2) * P when CLKGDV is even

D = CLKRX high pulse width = T/2 when CLKGDV is odd or zero and = (CLKGDV/2 + 1) * P when CLKGDV is even

(4)See the TMS320VC5501/5502/5503/5507/5509/5510 DSP Multichannel Buffered Serial Port (McBSP) Reference Guide (literature number SPRU592) for a description of the DX enable (DXENA) and data delay features of the McBSP.

160

Specifications

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CLKR

FSR (Int)

FSR (Ext)

DR (RDATDLY=00b)

DR (RDATDLY=01b)

DR (RDATDLY=10b)

CLKX

FSX (Int)

FSX (Ext)

DX (XDATDLY=00b)

DX (XDATDLY=01b)

DX (XDATDLY=10b)

		TMS320VC5502
		Fixed-Point Digital Signal Processor
		SPRS166J –APRIL 2001 –REVISED AUGUST 2006
	M1, M11
	M2, M12	M13
	M3, M12	M13
	M3, M12
M4	M4	M14
	M4

M15

M16

M17

M18

Bit (n-1)	(n-2)	(n-3)	(n-4)
M17	M18
	M18
	Bit (n-1)	(n-2)	(n-3)
	M17		M18
			M18
		Bit (n-1)	(n-2)
Figure 5-32. McBSP Receive Timings
M1, M11
M2, M12		M13
		M13	M14
	M3, M12		M14
	M3, M12
M5	M5

M19 M20

	M9		M7
M10			M7
M10
Bit 0	Bit (n−1)	(n−2)	(n−3)	(n−4)
	M8		M7
	M8
Bit 1	Bit 0	Bit (n−1)	(n−2)	(n−3)
M6			M7
M6		M8
		M8
Bit 2	Bit 1	Bit 0	Bit (n−1)	(n−2)

A.This figure does not include first or last frames. For first frame, no data will be present before frame synchronization. For last frame, no data will be present after frame synchronization.

Figure 5-33. McBSP Transmit Timings

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161

TMS320VC5502

Fixed-Point Digital Signal Processor

www.ti.com

SPRS166J –APRIL 2001 –REVISED AUGUST 2006

5.15.2McBSP General-Purpose I/O Timings

Table 5-33 and Table 5-34 assume testing over recommended operating conditions (see Figure 5-34).

Table 5-33. McBSP General-Purpose I/O Timing Requirements

				VC5502-200
NO.				VC5502-300	UNIT
				MIN MAX
M22	t	su(MGPIO-COH)	Setup time, MGPIOx input mode before CLKOUT high(1)(2)	4	ns
		su(MGPIO-COH)
M23	t	h(COH-MGPIO)	Hold time, MGPIOx input mode after CLKOUT high(1)(2)	0	ns

(1)MGPIOx refers to CLKRx, FSRx, DRx, CLKXx, or FSXx when configured as a general-purpose input.

(2)In this case, CLKOUT reflects SYSCLK2. The CLKOUT Selection Register (CLKOUTSR) can be programmed to select SYSCLK2 as CLKOUT.

Table 5-34. McBSP General-Purpose I/O Switching Characteristics

			VC5502-200
NO.		PARAMETER	VC5502-300		UNIT
			MIN	MAX
M21 t	d(COH-MGPIO)	Delay time, CLKOUT high to MGPIOx output mode(1)(2)	0	6	ns
	d(COH-MGPIO)

(1)In this case, CLKOUT reflects SYSCLK2. The CLKOUT Selection Register (CLKOUTSR) can be programmed to select SYSCLK2 as CLKOUT.

(2)MGPIOx refers to CLKRx, FSRx, CLKXx, FSXx, or DXx when configured as a general-purpose output.

M22

CLKOUT

M21

M23

MGPIO

Input Mode

(see Note A)

MGPIO

Output Mode

(see Note B)

A.MGPIOx refers to CLKRx, FSRx, DRx, CLKXx, or FSXx when configured as a general-purpose input.

B.MGPIOx refers to CLKRx, FSRx, CLKXx, FSXx, or DXx when configured as a general-purpose output.

Figure 5-34. McBSP General-Purpose I/O Timings

162

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