TMS320VC5502
Fixed-Point Digital Signal Processor
www.ti.com
SPRS166J –APRIL 2001 –REVISED AUGUST 2006
5.14 TIM0/TIM1/WDTOUT Timings
Table 5-26 and Table 5-27 assume testing over recommended operating conditions(see Figure 5-28 and Figure 5-29).
5.14.1TIM0/TIM1/WDTOUT Timer Pin Timings
Table 5-26. TIM0/TIM1/WDTOUT Pins Configured as Timer Input Pins Timing Requirements(1)
|
|
|
VC5502-200 |
|
NO. |
|
|
VC5502-300 |
UNIT |
|
|
|
MIN MAX |
|
T4 |
tw(TIML) |
Pulse width, TIM0/TIM1/WDTOUT low |
4P |
ns |
T5 |
tw(TIMH) |
Pulse width, TIM0/TIM1/WDTOUT high |
4P |
ns |
(1)P = (Divider1 Ratio)/(CPU Clock Frequency) in ns. For example, when running parts at 300 MHz with the fast peripheral domain at 1/2 the CPU clock frequency, use P = 2/300 MHz = 6.66 ns.
Table 5-27. TIM0/TIM1/WDTOUT Pins Configured as Timer Output Pins Switching Characteristics
|
|
|
|
VC5502-200 |
|
|
NO. |
|
|
PARAMETER |
VC5502-300 |
UNIT |
|
|
|
|
|
MIN |
MAX |
|
T1 |
t |
d(COH-TIMH) |
Delay time, CLKOUT high to TIM0/TIM1/WDTOUT high(1) |
0 |
6 |
ns |
|
|
|
|
|
|
|
T2 |
t |
d(COH-TIML) |
Delay time, CLKOUT high to TIM0/TIM1/WDTOUT low(1) |
0 |
7 |
ns |
|
|
|
|
|
|
|
T3 |
t |
w(TIM) |
Pulse duration, TIM0/TIM1/WDTOUT |
P(2) |
|
ns |
(1)In this case, CLKOUT reflects SYSCLK1. The CLKOUT Selection Register (CLKOUTSR) can be programmed to select SYSCLK1 as CLKOUT.
(2)P = (Divider1 Ratio)/(CPU Clock Frequency) in ns. For example, when running parts at 300 MHz with the fast peripheral domain at 1/2 the CPU clock frequency, use P = 2/300 MHz = 6.66 ns.
T5
T4
TIM0/TIM1/WDTOUT as Input
Figure 5-28. TIM0/TIM1/WDTOUT Timings When Configured as Timer Input Pins
CLKOUT
T2
T1
TIM0/TIM1/WDTOUT
as Output
T3
Figure 5-29. TIM0/TIM1/WDTOUT Timings When Configured as Timer Output Pins
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Specifications |
155 |
TMS320VC5502
Fixed-Point Digital Signal Processor
www.ti.com
SPRS166J –APRIL 2001 –REVISED AUGUST 2006
5.14.2TIM0/TIM1/WDTOUT General-Purpose I/O Timings
Table 5-28 and Table 5-29 assume testing over recommended operating conditions (see Figure 5-30).
Table 5-28. TIM0/TIM1/WDTOUT General-Purpose I/O Timing Requirements(1)
NO.
T9 tsu(TIM0GPIO-COH)
T10 th(COH-TIM0GPIO)
T11 tsu(TIM1GPIO-COH)
T12 th(COH-TIM1GPIO)
T13 tsu(WDTGPIO-COH)
T14 th(COH-WDTGPIO)
|
VC5502-200 |
|
|
VC5502-300 |
UNIT |
|
MIN MAX |
|
Setup time, TIM0-GPIO input mode before CLKOUT high |
5 |
ns |
Hold time, TIM0-GPIO input mode after CLKOUT high |
0 |
ns |
Setup time, TIM1-GPIO input mode before CLKOUT high |
5 |
ns |
Hold time, TIM1-GPIO input mode after CLKOUT high |
0 |
ns |
Setup time, WDTOUT-GPIO input mode before CLKOUT high |
5 |
ns |
Hold time, WDTOUT-GPIO input mode after CLKOUT high |
0 |
ns |
(1)In this case, CLKOUT reflects SYSCLK1. The CLKOUT Selection Register (CLKOUTSR) can be programmed to select SYSCLK1 as CLKOUT.
Table 5-29. TIM0/TIM1/WDTOUT General-Purpose I/O Switching Characteristics(1)
|
|
|
VC5502-200 |
|
NO. |
|
PARAMETER |
VC5502-300 |
UNIT |
|
|
|
MIN MAX |
|
T6 |
td(COH-TIM0GPIO) |
Delay time, CLKOUT high to TIM0-GPIO output mode |
10 |
ns |
T7 |
td(COH-TIM1GPIO) |
Delay time, CLKOUT high to TIM1-GPIO output mode |
10 |
ns |
T8 |
td(COH-WDTGPIO) |
Delay time, CLKOUT high to WDTOUT-GPIO output mode |
10 |
ns |
(1)In this case, CLKOUT reflects SYSCLK1. The CLKOUT Selection Register (CLKOUTSR) can be programmed to select SYSCLK1 as CLKOUT.
156 |
Specifications |
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TMS320VC5502
Fixed-Point Digital Signal Processor
www.ti.com
SPRS166J –APRIL 2001 –REVISED AUGUST 2006
CLKOUT
T9
T10
TIM0 GPIO
Input Mode
T6
TIM0 GPIO
Output Mode
T11
T12
TIM1 GPIO
Input Mode
T7
TIM1 GPIO
Output Mode
T13
T14
WDTOUT GPIO
Input Mode
T8
WDTOUT GPIO
Output Mode
Figure 5-30. TIM0/TIM1/WDTOUT General-Purpose I/O Timings
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Specifications |
157 |
TMS320VC5502
Fixed-Point Digital Signal Processor
www.ti.com
SPRS166J –APRIL 2001 –REVISED AUGUST 2006
5.14.3TIM0/TIM1/WDTOUT Interrupt Timings
Table 5-30 assumes testing over recommended operating conditions (see Figure 5-31).
Table 5-30. TIM0/TIM1/WDTOUT Interrupt Timing Requirements(1) (2)
|
VC5502-200 |
|
NO. |
VC5502-300 |
UNIT |
|
MIN MAX |
|
T15 tsu(TIM0L-COH)
T16 th(COH-TIM0L)
T17 
tw(TIM0L)
T18 tsu(TIM1L-COH)
T19 th(COH-TIM1L)
T20 
tw(TIM1L)
T21 tsu(WDTL-COH)
T22 
th(COH-WDTL)
T23 tw(WDTL)
Setup time, TIM0 low(3) before CLKOUT rising edge |
5 |
ns |
Hold time, TIM0 low(3) after CLKOUT rising edge |
0 |
ns |
Pulse width, TIM0 low(3) |
P |
ns |
Setup time, TIM1 low(3) before CLKOUT rising edge |
5 |
ns |
Hold time, TIM1 low(3) after CLKOUT rising edge |
0 |
ns |
Pulse width, TIM1 low(3) |
P |
ns |
Setup time, WDTOUT low(3) before CLKOUT rising edge |
5 |
ns |
Hold time, WDTOUT low(3) after CLKOUT rising edge |
0 |
ns |
Pulse width, WDTOUT low(3) |
P |
ns |
(1)In this case, CLKOUT reflects SYSCLK1. The CLKOUT Selection Register (CLKOUTSR) can be programmed to select SYSCLK1 as CLKOUT.
(2)P = (Divider1 Ratio)/(CPU Clock Frequency) in ns. For example, when running parts at 300 MHz with the fast peripheral domain at 1/2 the CPU clock frequency, use P = 2/300 MHz = 6.66 ns.
(3)An interrupt can be triggered by setting the timer pins high or low, depending on the setting of the TIN1INV bit in the GPIO Interrupt Control Register (GPINT). Refer to the TMS320VC5501/5502 DSP Timers Reference Guide (literature number SPRU618) for more information on the interrupt capability of the timer pins.
CLKOUT
T15 
T16
T17
TIM0
T18 
T19
T20
TIM1
T21 
T22
T23
WDTOUT
Figure 5-31. TIM0/TIM1/WDTOUT Interrupt Timings
158 |
Specifications |
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