TMS320VC5502
Fixed-Point Digital Signal Processor
www.ti.com
SPRS166J –APRIL 2001 –REVISED AUGUST 2006
5.11 XF Timings
Table 5-21 assumes testing over recommended operating conditions (see Figure 5-25).
Table 5-21. XF Switching Characteristics
|
|
|
VC5502-200 |
|
NO. |
|
PARAMETER |
VC5502-300 |
UNIT |
|
|
|
MIN MAX |
|
|
td(XF) |
Delay time, CLKOUT high to XF high(1) |
0 |
5 |
X1 |
Delay time, CLKOUT high to XF low(1) |
0 |
ns |
|
|
|
6 |
||
(1)In this case, CLKOUT refers to the CPU clock. Since CLKOUT cannot be programmed to reflect the CPU clock, there might be an extra delay of a certain number of CPU clocks based on the ratio between the system clock shown on CLKOUT and the CPU clock. For example, if SYSCLK2 is shown on CLKOUT and SYSCLK2 is programmed to be half the CPU clock, there might be an extra delay of one CPU clock period between the transition of CLKOUT and the specified timing. If system clock is programmed to be one-fourth of the CPU clock, there might be an extra delay of 1, 2, or 3 CPU clocks between the transition of CLKOUT and the specified timing. The extra delay must be taken into account when considering the MAX value for the timing under question. Note that if the CPU clock and the system clock shown on CLKOUT are operating at the same frequency, there will be no extra delay in the specified timing.
CLKOUT
X1
XF
(A ) The figure shows the case in which CLKOUT is programmed to show a system clock that is operating at the same frequency as the CPU clock.
Figure 5-25. XF Timings
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Specifications |
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TMS320VC5502
Fixed-Point Digital Signal Processor
www.ti.com
SPRS166J –APRIL 2001 –REVISED AUGUST 2006
5.12 General-Purpose Input/Output (GPIOx) Timings
Table 5-22 and Table 5-23 assume testing over recommended operating conditions(see Figure 5-26).
Table 5-22. GPIO Pins Configured as Inputs Timing Requirements
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|
|
|
VC5502-200 |
|
NO. |
|
|
|
VC5502-300 |
UNIT |
|
|
|
|
MIN MAX |
|
G2 |
t |
su(GPIO-COH) |
Setup time, GPIOx input valid before CLKOUT high(1) |
5 |
ns |
|
|
|
|
|
|
G3 |
t |
h(COH-GPIO) |
Hold time, GPIOx input valid after CLKOUT high(1) |
0 |
ns |
(1)In this case, CLKOUT reflects SYSCLK1. The CLKOUT Selection Register (CLKOUTSR) can be programmed to select SYSCLK1 as CLKOUT.
Table 5-23. GPIO Pins Configured as Outputs Switching Characteristics
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|
|
VC5502-200 |
|
|
NO. |
|
PARAMETER |
VC5502-300 |
UNIT |
|
|
|
|
MIN |
MAX |
|
G1 t |
d(COH-GPIO) |
Delay time, CLKOUT high to GPIOx output change(1) |
0 |
8 |
ns |
|
|
|
|
|
|
(1)In this case, CLKOUT reflects SYSCLK1. The CLKOUT Selection Register (CLKOUTSR) can be programmed to select SYSCLK1 as CLKOUT.
CLKOUT
G2
G3
GPIOx
Input Mode
G1
GPIOx
Output Mode
Figure 5-26. General-Purpose Input/Output (GPIOx) Signal Timings
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Specifications |
153 |
TMS320VC5502
Fixed-Point Digital Signal Processor
www.ti.com
SPRS166J –APRIL 2001 –REVISED AUGUST 2006
5.13 Parallel General-Purpose Input/Output (PGPIOx) Timings
Table 5-24 and Table 5-25 assume testing over recommended operating conditions(see Figure 5-27).
Table 5-24. PGPIO Pins Configured as Inputs Timing Requirements
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|
|
|
VC5502-200 |
|
NO. |
|
|
|
VC5502-300 |
UNIT |
|
|
|
|
MIN MAX |
|
PG2 |
t |
su(PGPIO-COH) |
Setup time, PGPIOx input valid before CLKOUT high(1) |
6 |
ns |
|
|
|
|
|
|
PG3 |
t |
h(COH-PGPIO) |
Hold time, PGPIOx input valid after CLKOUT high(1) |
0 |
ns |
(1)In this case, CLKOUT reflects SYSCLK1. The CLKOUT Selection Register (CLKOUTSR) can be programmed to select SYSCLK1 as CLKOUT.
Table 5-25. PGPIO Pins Configured as Outputs Switching Characteristics
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|
|
VC5502-200 |
|
|
NO. |
|
PARAMETER |
VC5502-300 |
UNIT |
|
|
|
|
MIN |
MAX |
|
PG1 t |
d(COH-PGPIO) |
Delay time, CLKOUT high to PGPIOx output change(1) |
0 |
10 |
ns |
|
|
|
|
|
|
(1)In this case, CLKOUT reflects SYSCLK1. The CLKOUT Selection Register (CLKOUTSR) can be programmed to select SYSCLK1 as CLKOUT.
CLKOUT
PG2
PG3
PGPIOx
Input Mode
PG1
PGPIOx
Output Mode
Figure 5-27. Parallel General-Purpose Input/Output (PGPIOx) Signal Timings
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