TMS320VC5502
Fixed-Point Digital Signal Processor
www.ti.com
SPRS166J –APRIL 2001 –REVISED AUGUST 2006
5.7.3Synchronous DRAM Timings
Table 5-13 and Table 5-14 assume testing over recommended operating conditions (see Figure 5-13 through Figure 5-20).
Table 5-13. Synchronous DRAM Cycle Timing Requirements
|
|
VC5502-200 |
|
NO. |
|
VC5502-300 |
UNIT |
|
|
MIN MAX |
|
SD6 tsu(EDV-EKO1H) |
Setup time, read EMIF.Dx valid before ECLKOUT1 high |
2 |
ns |
SD7 th(EKO1H-EDV) |
Hold time, read EMIF.Dx valid after ECLKOUT1 high |
2 |
ns |
Table 5-14. Synchronous DRAM Cycle Switching Characteristics
NO.
SD1 td(EKO1H-CEV)
SD2 td(EKO1H-BEV)
SD3 td(EKO1H-BEIV)
SD4 td(EKO1H-EAV)
SD5 td(EKO1H-EAIV)
SD8 td(EKO1H-CASV)
SD9 td(EKO1H-EDV)
SD10 td(EKO1H-EDIV)
SD11 td(EKO1H-WEV)
SD12 td(EKO1H-RASV)
SD13 td(EKO1H-CKEV)
|
VC5502-200 |
|
|
PARAMETER |
VC5502-300 |
UNIT |
|
|
MIN |
MAX |
|
Delay time, ECLKOUT1 high to EMIF.CEx valid/invalid |
0.8 |
7 |
ns |
Delay time, ECLKOUT1 high to EMIF.BEx valid |
|
7 |
ns |
Delay time, ECLKOUT1 high to EMIF.BEx invalid |
0.8 |
|
ns |
Delay time, ECLKOUT1 high to EMIF.Ax valid |
|
7 |
ns |
Delay time, ECLKOUT1 high to EMIF.Ax invalid |
0.8 |
|
ns |
Delay time, ECLKOUT1 high to EMIF.SDCAS valid |
0.8 |
7 |
ns |
Delay time, ECLKOUT1 high to EMIF.Dx valid |
|
7 |
ns |
Delay time, ECLKOUT1 high to EMIF.Dx invalid |
0.8 |
|
ns |
Delay time, ECLKOUT1 high to EMIF.SDWE valid |
0.8 |
7 |
ns |
Delay time, ECLKOUT1 high to EMIF.SDRAS valid |
0.8 |
7 |
ns |
Delay time, ECLKOUT1 high to EMIF.SDCKE valid |
0.8 |
7 |
ns |
Submit Documentation Feedback |
Specifications |
143 |
TMS320VC5502
Fixed-Point Digital Signal Processor
www.ti.com
SPRS166J –APRIL 2001 –REVISED AUGUST 2006 |
|
|
|
|
|
|
|
|
READ |
|
|
|
|
|
|
ECLKOUT1 |
|
|
|
|
|
|
|
|
SD1 |
SD1 |
|
|
|
|
|
|
|
|
|
|
|
|
|
EMIF.CEx |
|
|
|
|
|
|
|
|
|
SD2 |
|
|
|
SD3 |
|
EMIF.BE[3:0] |
|
BE1 |
BE2 |
BE3 |
BE4 |
|
|
|
SD4 |
SD5 |
|
|
|
|
|
|
|
|
|
|
|
|
|
EMIF.A[21:13] |
Bank |
|
|
|
|
|
|
|
SD4 |
SD5 |
|
|
|
|
|
|
|
|
|
|
|
|
|
EMIF.A[11:2] |
Column |
|
|
|
|
|
|
|
SD4 |
SD5 |
|
|
|
|
|
|
|
|
|
|
|
|
|
EMIF.A12 |
|
|
|
|
|
|
|
|
|
|
SD6 |
|
SD7 |
|
|
|
|
|
|
|
|
|
|
EMIF.D[31:0] |
|
|
|
D1 |
D2 |
D3 |
D4 |
EMIF.AOE/SOE/SDRAS |
|
|
|
|
|
|
|
(see Note A) |
SD8 |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
SD8
EMIF.ARE/SADS/SDCAS/SRE (see Note A)
EMIF.AWE/SWE/SDWE
(see Note A)
A.EMIF.ARE/SADS/SDCAS/SRE, EMIF.AWE/SWE/SDWE, and EMIF.AOE/SOE/SDRAS operate as EMIF.SDCAS, EMIF.SDWE, and EMIF.SDRAS, respectively, during SDRAM accesses.
Figure 5-13. SDRAM Read Command (CAS Latency 3)
|
WRITE |
|
|
|
ECLKOUT1 |
|
|
|
|
|
SD1 |
SD1 |
|
|
|
|
|
|
|
EMIF.CEx |
|
|
|
|
|
SD2 |
SD2 |
|
SD3 |
EMIF.BE[3:0] |
BE1 |
BE2 |
BE3 |
BE4 |
|
SD4 |
SD5 |
|
|
|
|
|
|
|
EMIF.A[21:13] |
Bank |
|
|
|
|
SD4 |
SD5 |
|
|
|
|
|
|
|
EMIF.A[11:2] |
Column |
|
|
|
|
SD4 |
SD5 |
|
|
|
|
|
|
|
EMIF.A12 |
|
|
|
|
|
SD9 |
SD9 |
|
SD10 |
|
|
|
||
EMIF.D[31:0] |
D1 |
D2 |
D3 |
D4 |
EMIF.AOE/SOE/SDRAS |
|
|
|
|
(see Note A) |
SD8 |
SD8 |
|
|
EMIF.ARE/SADS/SDCAS/SRE |
|
|
|
|
|
|
|
|
|
(see Note A) |
|
|
|
|
SD11
SD11
EMIF.AWE/SWE/SDWE
(see Note A)
A.EMIF.ARE/SADS/SDCAS/SRE, EMIF.AWE/SWE/SDWE, and EMIF.AOE/SOE/SDRAS operate as EMIF.SDCAS, EMIF.SDWE, and EMIF.SDRAS, respectively, during SDRAM accesses.
Figure 5-14. SDRAM Write Command
144 |
Specifications |
Submit Documentation Feedback |
TMS320VC5502
Fixed-Point Digital Signal Processor
www.ti.com
SPRS166J –APRIL 2001 –REVISED AUGUST 2006
|
ACTV |
|
ECLKOUT1 |
|
|
|
SD1 |
SD1 |
|
|
|
EMIF.CEx |
|
|
EMIF.BE[3:0] |
|
|
|
SD4 |
SD5 |
|
|
|
EMIF.A[21:13] |
Bank Activate |
|
|
SD4 |
SD5 |
|
|
|
EMIF.A[11:2] |
Row Address |
|
|
SD4 |
SD5 |
|
|
|
EMIF.A12 |
Row Address |
|
EMIF.D[31:0] |
|
|
EMIF.AOE/SOE/SDRAS |
SD12 |
SD12 |
(see Note A) |
|
|
|
|
|
EMIF.ARE/SADS/SDCAS/SRE |
|
|
(see Note A) |
|
|
EMIF.AWE/SWE/SDWE
(see Note A)
A.EMIF.ARE/SADS/SDCAS/SRE, EMIF.AWE/SWE/SDWE, and EMIF.AOE/SOE/SDRAS operate as EMIF.SDCAS, EMIF.SDWE, and EMIF.SDRAS, respectively, during SDRAM accesses.
Figure 5-15. SDRAM ACTV Command
DCAB
ECLKOUT1
SD1
SD1
EMIF.CEx
EMIF.BE[3:0]
EMIF.A[21:13, 11:2]
SD4 |
SD5 |
|
EMIF.A12 
EMIF.D[31:0]
SD12
SD12
EMIF.AOE/SOE/SDRAS (see Note A)
EMIF.ARE/SADS/SDCAS/SRE |
|
(see Note A) |
SD11 |
|
SD11
EMIF.AWE/SWE/SDWE (see Note A)
A.EMIF.ARE/SADS/SDCAS/SRE, EMIF.AWE/SWE/SDWE, and EMIF.AOE/SOE/SDRAS operate as EMIF.SDCAS, EMIF.SDWE, and EMIF.SDRAS, respectively, during SDRAM accesses.
Figure 5-16. SDRAM DCAB Command
Submit Documentation Feedback |
Specifications |
145 |
TMS320VC5502
Fixed-Point Digital Signal Processor
www.ti.com
SPRS166J –APRIL 2001 –REVISED AUGUST 2006
|
DEAC |
|
ECLKOUT1 |
|
|
|
SD1 |
SD1 |
|
|
|
EMIF.CEx |
|
|
EMIF.BE[3:0] |
|
|
|
SD4 |
SD5 |
|
|
|
EMIF.A[21:13] |
Bank |
|
EMIF.A[11:2] |
|
|
|
SD4 |
SD5 |
|
|
|
EMIF.A12 |
|
|
EMIF.D[31:0] |
|
|
EMIF.AOE/SOE/SDRAS |
SD12 |
SD12 |
|
||
|
|
|
(see Note A) |
|
|
EMIF.ARE/SADS/SDCAS/SRE |
|
|
(see Note A) |
SD11 |
|
|
SD11 |
|
EMIF.AWE/SWE/SDWE |
|
|
|
|
|
(see Note A) |
|
|
A.EMIF.ARE/SADS/SDCAS/SRE, EMIF.AWE/SWE/SDWE, and EMIF.AOE/SOE/SDRAS operate as EMIF.SDCAS, EMIF.SDWE, and EMIF.SDRAS, respectively, during SDRAM accesses.
Figure 5-17. SDRAM DEAC Command
|
|
REFR |
|
ECLKOUT1 |
|
|
|
|
SD1 |
SD1 |
|
|
|
||
EMIF.CEx |
|
|
|
EMIF.BE[3:0] |
|
|
|
EMIF.A[21:13, 11:2] |
|
|
|
EMIF.A12 |
|
|
|
EMIF.D[31:0] |
|
|
|
|
SD12 |
SD12 |
|
EMIF.AOE/SOE/SDRAS |
|
||
|
|
||
(see Note A) |
SD8 |
|
|
EMIF.ARE/SADS/SDCAS/SRE |
SD8 |
||
|
|||
|
|
||
(see Note A) |
|
|
EMIF.AWE/SWE/SDWE
(see Note A)
A.EMIF.ARE/SADS/SDCAS/SRE, EMIF.AWE/SWE/SDWE, and EMIF.AOE/SOE/SDRAS operate as EMIF.SDCAS, EMIF.SDWE, and EMIF.SDRAS, respectively, during SDRAM accesses.
Figure 5-18. SDRAM REFR Command
146 |
Specifications |
Submit Documentation Feedback |
TMS320VC5502
Fixed-Point Digital Signal Processor
www.ti.com
SPRS166J –APRIL 2001 –REVISED AUGUST 2006
|
MRS |
|
|
ECLKOUT1 |
|
|
|
|
SD1 |
SD1 |
|
|
|
||
EMIF.CEx |
|
|
|
EMIF.BE[3:0] |
|
|
|
|
SD4 |
SD5 |
|
|
|
||
EMIF.A[21:2] |
MRS value |
|
|
EMIF.D[31:0] |
|
|
|
|
SD12 |
SD12 |
|
EMIF.AOE/SOE/SDRAS |
|
||
|
|
||
(see Note A) |
SD8 |
|
|
EMIF.ARE/SADS/SDCAS/SRE |
SD8 |
||
|
|||
|
|
||
(see Note A) |
|
|
|
|
SD11 |
SD11 |
|
EMIF.AWE/SWE/SDWE |
|
||
|
|
||
(see Note A) |
|
|
A.EMIF.ARE/SADS/SDCAS/SRE, EMIF.AWE/SWE/SDWE, and EMIF.AOE/SOE/SDRAS operate as EMIF.SDCAS, EMIF.SDWE, and EMIF.SDRAS, respectively, during SDRAM accesses.
Figure 5-19. SDRAM MRS Command
≥ TRAS cycles
|
|
Self Refresh |
|
|
|
|
End Self-Refresh |
||||
|
|
|
|
|
|
||||||
|
|
|
|
|
|
|
|
|
|
|
|
ECLKOUT1
EMIF.CEx
EMIF.BE[3:0]
EMIF.A[21:13, 11:2]
EMIF.A12
EMIF.D[31:0]
EMIF.AOE/SOE/SDRAS
(see Note A)
EMIF.ARE/SADS/SDCAS/SRE
(see Note A)
EMIF.AWE/SWE/SDWE |
|
(see Note A) |
SD13 |
SD13 
EMIF.SDCKE
A.EMIF.ARE/SADS/SDCAS/SRE, EMIF.AWE/SWE/SDWE, and EMIF.AOE/SOE/SDRAS operate as EMIF.SDCAS, EMIF.SDWE, and EMIF.SDRAS, respectively, during SDRAM accesses.
Figure 5-20. SDRAM Self-Refresh Timings
Submit Documentation Feedback |
Specifications |
147 |