TMS320VC5502
Fixed-Point Digital Signal Processor
www.ti.com
SPRS166J –APRIL 2001 –REVISED AUGUST 2006
C8
C9
C7
CLKIN
C3
C6
C1
C5
C4
CLKOUT 
Bypass Mode
(A ) The waveform relationship of CLKIN to CLKOUT depends on the multiply and divide factors chosen for the APLL synthesis and on the system clock selected to drive CLKOUT. The waveform relationship shown in this figure is intended to illustrate the timing parameters only and may differ based on configuration.
Figure 5-4. External Multiply-by-N Clock Timings
5.6.5EMIF Clock Options
Table 5-6 through Table 5-8 assume testing over recommended operating conditions (see Figure 5-5 through Figure 5-7).
Table 5-6. EMIF Timing Requirements for ECLKIN(1) (2)
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VC5502-200 |
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NO. |
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|
VC5502-300 |
UNIT |
|
|
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|
MIN |
MAX |
|
E7 |
tc(EKI) |
Cycle time, ECLKIN |
10 |
16P |
ns |
E8 |
tw(EKIH) |
Pulse duration, ECLKIN high |
0.4 * tc(EKI) |
|
ns |
E9 |
tw(EKIL) |
Pulse duration, ECLKIN low |
0.4 * tc(EKI) |
|
ns |
E10 |
tt(EKI) |
Transition time, ECLKIN |
|
2 |
ns |
(1)P = 1/CPU clock frequency in ns. For example, when running parts at 300 MHz, use P = 3.33 ns.
(2)The reference points for the rise and fall transitions are measured at VIL MAX and VIHMIN.
Table 5-7. EMIF Switching Characteristics for ECLKOUT1(1) (2) (3)
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VC5502-200 |
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NO. |
PARAMETER |
VC5502-300 |
UNIT |
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MIN |
MAX |
|
E1 tc(EKO1)
E2 tw(EKO1H)
E3 tw(EKO1L)
E4 tt(EKO1)
E5 td(EKIH-EKO1H)
E6 td(EKIL-EKO1L)
Cycle time, ECLKOUT1 |
E – 1 |
E + 1 |
ns |
Pulse duration, ECLKOUT1 high |
EH – 1 |
EH + 1 |
ns |
Pulse duration, ECLKOUT1 low |
EL – 1 |
EL + 1 |
ns |
Transition time, ECLKOUT1 |
|
1 |
ns |
Delay time, ECLKIN high to ECLKOUT1 high |
3 |
13 |
ns |
Delay time, ECLKIN low to ECLKOUT1 low |
3 |
13 |
ns |
(1)The reference points for the rise and fall transitions are measured at VOL MAX and VOH MIN.
(2)E = the EMIF input clock (CPU clock, CPU/2 clock, or CPU/4 clock) period in ns for EMIF.
(3)EH is the high period of E (EMIF input clock period) in ns and EL is the low period of E (EMIF input clock period) in ns for EMIF.
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Specifications |
135 |
TMS320VC5502
Fixed-Point Digital Signal Processor
www.ti.com
SPRS166J –APRIL 2001 –REVISED AUGUST 2006
E7
E10
E8
ECLKIN
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E9 |
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E10 |
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Figure 5-5. ECLKIN Timings for EMIF |
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ECLKIN |
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E1 |
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E6 |
E2 |
E4 |
E4 |
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E5 |
E3 |
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ECLKOUT1 |
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Figure 5-6. ECLKOUT1 Timings for EMIF Module
Table 5-8. EMIF Switching Characteristics for ECLKOUT2(1) (2)
NO. |
|
PARAMETER |
E11 |
tc(EKO2) |
Cycle time, ECLKOUT2 |
E12 |
tw(EKO2H) |
Pulse duration, ECLKOUT2 high |
E13 |
tw(EKO2L) |
Pulse duration, ECLKOUT2 low |
E14 |
tt(EKO2) |
Transition time, ECLKOUT2 |
E15 |
td(EKIH-EKO2H) |
Delay time, ECLKIN high to ECLKOUT2 high |
E16 |
td(EKIH-EKO2L) |
Delay time, ECLKIN high to ECLKOUT2 low |
(1)The reference points for the rise and fall transitions are measured at VOL MAX and VOH MIN.
(2)E = the EMIF input clock (CPU clock, CPU/2 clock, or CPU/4 clock) period in ns for EMIF. N = the EMIF input clock divider; N = 1, 2, or 4.
E15 |
E16 |
ECLKIN
E11
E12
E13
ECLKOUT2
VC5502-200 |
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|
VC5502-300 |
UNIT |
|
MIN |
MAX |
|
NE – 1 |
NE + 1 |
ns |
0.5NE – 1 |
0.5NE + 1 |
ns |
0.5NE – 1 |
0.5NE + 1 |
ns |
|
1 |
ns |
3 |
13 |
ns |
3 |
13 |
ns |
E14 
E14 
Figure 5-7. ECLKOUT2 Timings for EMIF Module
136 |
Specifications |
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