TMS320VC5502
Fixed-Point Digital Signal Processor
www.ti.com
SPRS166J –APRIL 2001 –REVISED AUGUST 2006
5 Specifications
5.1Electrical Specifications
This section provides the absolute maximum ratings and the recommended operating conditions for the TMS320VC5502 DSP.
All electrical and switching characteristics in this data manual are valid over the recommended operating conditions unless otherwise specified.
5.2Absolute Maximum Ratings Over Operating Case Temperature Range (Unless Otherwise Noted)(1) (2) (3)
Supply voltage I/O range, DVDD |
–0.3 V to 4.0 V |
Supply voltage core range, CVDD |
–0.3 V to 2.0 V |
Input voltage range, VI |
–0.3 V to 4.5 V |
Output voltage range, Vo |
–0.3 V to 4.5 V |
Operating case temperature range, TC |
–40°C to 85°C |
Storage temperature range, Tstg |
–55°C to 150°C |
(1)Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2)All supply voltage values (core and I/O) are with respect to VSS.
(3)Figure 5-1 provides the test load circuit values for a 3.3-V device. Measured timing information contained in this data manual is based on the test load setup and conditions shown in Figure 5-1.
5.3Recommended Operating Conditions
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MIN |
NOM |
MAX |
UNIT |
DVDD |
Device supply voltage, I/O |
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3.0 |
3.3 |
3.6 |
V |
CVDD |
Device supply voltage, core |
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1.20 |
1.26 |
1.32 |
V |
PVDD |
Device supply voltage, PLL |
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3.0 |
3.3 |
3.6 |
V |
VSS |
Supply voltage, GND |
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0 |
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V |
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Hysteresis inputs |
2.2 |
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DVDD + 0.3 |
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DVDD = 3.0 – 3.6 V |
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VIH |
High-level input voltage, I/O |
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V |
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All other inputs |
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2 |
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DVDD + 0.3 |
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DVDD = 3.0 – 3.6 V |
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Hysteresis inputs |
–0.3 |
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0.8 |
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DVDD = 3.0 – 3.6 V |
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VIL |
Low-level input voltage, I/O |
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V |
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All other inputs |
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– 0.3 |
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0.8 |
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DVDD = 3.0 – 3.6 V |
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IOH |
High-level output current |
All outputs |
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–300 |
µA |
IOL |
Low-level output current |
All outputs |
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1.5 |
mA |
TC |
Operating case temperature |
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–40 |
|
85 |
°C |
128 |
Specifications |
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TMS320VC5502
Fixed-Point Digital Signal Processor
www.ti.com
SPRS166J –APRIL 2001 –REVISED AUGUST 2006
5.4Electrical Characteristics Over Recommended Operating Case Temperature Range (Unless Otherwise Noted)
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PARAMETER |
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TEST CONDITIONS |
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VOH |
High-level output voltage |
DVDD = 3.3 ± 0.3 V, |
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IOH = MAX |
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VOL |
Low-level output voltage |
IOL = MAX |
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Output-only or input/output pins |
Bus holders enabled |
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Input current for |
DVDD = MAX, |
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with bus holders |
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I |
outputs in high |
VO = VSS to DVDD |
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IZ |
impedance |
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All other output-only or |
DVDD = MAX, |
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input/output pins |
VI = VSS to DVDD |
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Input pins with internal pulldown |
DVDD = MAX, |
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V = V |
to DV |
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I SS |
DD |
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X2/CLKIN |
DVDD = MAX, |
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VI = VSS to DVDD |
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II |
Input current |
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Pullup enabled |
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Input pins with internal pullup |
DVDD = MAX, |
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VI = VSS to DVDD |
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All other input-only pins |
DVDD = MAX, |
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VI = VSS to DVDD |
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I |
CV |
supply current(1) |
CVDD = Nominal |
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CPU clock = 300 MHz |
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DDC |
DD |
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TC = 25°C |
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I |
DV |
supply current(1) |
DVDD = Nominal |
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CPU clock = 300 MHz |
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DDD |
DD |
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TC = 25°C |
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I |
PV |
supply current(1) |
PVDD = Nominal |
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20-MHz clock input, |
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DDP |
DD |
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APLL mode = x15 |
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Ci |
Input capacitance |
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Co |
Output capacitance |
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MIN |
TYP |
MAX |
UNIT |
2.4 |
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V |
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0.4 |
V |
–300 |
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300 |
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µA |
–5 |
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5 |
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–5 |
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300 |
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–50 |
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50 |
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µA |
–300 |
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5 |
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–5 |
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5 |
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239 |
mA |
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39 |
mA |
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11 |
mA |
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3 |
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pF |
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3 |
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pF |
(1)Current draw is highly application-dependent. The power numbers quoted here are for the sample application described in the TMS320VC5501/02 Power Consumption Summary application report (literature number SPRA993). The spreadsheet provided with the application report can be used to estimate the power consumption for a particular application. The spreadsheet also contains the current consumption that can be expected when running the DSP in its idle configurations.
The sample application can be summarized as follows:
∙Case temperature: 25°C
∙APLL: 300 MHz
∙CPU: 85% utilization
–Instruction cache enabled
–CLKOUT off
∙EMIF: 75 MHz, 118% utilization, 100% writes, 32 bits, 100% switching
–ECLKOUT1 and ECLKOUT2: Off
∙HPI: 5Mwords/second, 100% utilization, 100% writes, 100% switching
∙DMA:
–Channel 0: 35% utilization, 32-bit elements, 100% switching (for internal memory to external memory transfers)
–Channel 1: 1.56% utilization, 32-bit elements, 100% switching (for internal memory to McBSP0 transfers)
–Channel 2: 1.56% utilization, 32-bit elements, 100% switching (for McBSP1 to internal memory transfers)
–Channels 3 and 4: 0% utilization (reserved for UART transfers)
–Channel 5: 60% utilization (for internal memory to internal memory transfers using Watchdog Timer event)
∙McBSP0: 25 MHz, 100% utilization, 100% switching
∙Timer0: 5 MHz, 100% utilization, 100% switching
∙Timer1: 10 MHz, 100% utilization, 100% switching
∙WD Timer: 30 MHz, 100% utilization, 100% switching
∙UART: 9600 baud, 100% utilization
∙All other peripherals use 0 MHz, 0% utilization
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Specifications |
129 |
TMS320VC5502
Fixed-Point Digital Signal Processor
www.ti.com
SPRS166J –APRIL 2001 –REVISED AUGUST 2006
|
Tester Pin Electronics |
Data Sheet Timing Reference Point |
42 Ω |
3.5 nH |
Output |
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Transmission Line |
Under |
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Test |
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Z0 = 50 Ω |
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(see Note A) |
Device Pin |
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4.0 pF |
1.85 pF |
(see Note A) |
A.The data sheet provides timing at the device pin. For output timing analysis, the tester pin electronics and its transmission line effects must be taken into account. A transmission line with a delay of 2 ns or longer can be used to produce the desired transmission line effect. The transmission line is intended as a load only. It is not necessary to add or subtract the transmission line delay (2 ns or longer) from the data sheet timings.
Input requirements in this data sheet are tested with an input slew rate of < 4 Volts per nanosecond (4 V/ns) at the device pin.
Figure 5-1. 3.3-V Test Load Circuit
5.5Timing Parameter Symbology
Timing parameter symbols used in the timing requirements and switching characteristics tables are created in accordance with JEDEC Standard 100. To shorten the symbols, some of the pin names and other related terminology have been abbreviated as follows:
Lowercase subscripts and their meanings: |
Letters and symbols and their meanings: |
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a |
access time |
H |
High |
c |
cycle time (period) |
L |
Low |
d |
delay time |
V |
Valid |
dis |
disable time |
Z |
High impedance |
en |
enable time |
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f |
fall time |
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h |
hold time |
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r |
rise time |
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su |
setup time |
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t |
transition time |
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vvalid time
wpulse duration (width)
X |
Unknown, changing, or don'tcare level |
130 |
Specifications |
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