TMS320VC5502

Fixed-Point Digital Signal Processor

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SPRS166J –APRIL 2001 –REVISED AUGUST 2006

Table 3-75. Clock Controller Registers

Table 3-76. IDLE Control Registers

3.17 Interrupts

Vector-relative locations and priorities for all internal and external interrupts are shown in Table 3-77. For more information on setting up and using interrupts, please refer to the TMS320C55x DSP CPU Reference Guide (literature number SPRU371).

Table 3-77. Interrupt Table

(1)WDTINT is generated only when the WDT interrupt pin is connected to INT3 through the TSSR.

TMS320VC5502

Fixed-Point Digital Signal Processor

www.ti.com

3.17.1IFR and IER Registers

The Interrupt Enable Registers (IER0 and IER1) control which interrupts will be masked or enabled during normal operation. The Interrupt Flag Registers (IFR0 and IFR1) contain flags that indicate interrupts that are currently pending.

The Debug Interrupt Enable Registers (DBIER0 and DBIER1) are used only when the CPU is halted in the real-time emulation mode. If the CPU is running in real-time mode, the standard interrupt processing (IER0/1) is used and DBIER0/1 are ignored.

A maskable interrupt enabled in DBIER0/1 is defined as a time-critical interrupt. When the CPU is halted in the real-time mode, the only interrupts that are serviced are time-critical interrupts that are also enabled in an interrupt enable register (IER0 or IER1).

Write the DBIER0/1 to enable or disable time-critical interrupts. To enable an interrupt, set its corresponding bit. To disable an interrupt, clear its corresponding bit. Initialize these registers before using the real-time emulation mode.

A DSP hardware reset clears IFR0/1, IER0/1, and DBIER0/1 to 0. A software reset instruction clears IFR0/1 to 0 but does not affect IER0/1 and DBIER0/1.

TMS320VC5502

Fixed-Point Digital Signal Processor

www.ti.com

SPRS166J –APRIL 2001 –REVISED AUGUST 2006

The bit layouts of these registers for each interrupt are shown in Figure 3-51 and Figure 3-52. For more information on the IER, IFR, and DBIER registers, refer to the TMS320C55x DSP CPU Reference Guide (literature number SPRU371).

LEGEND: R = Read, W = Write, n = value at reset

(1)WDTINT is generated only when the WDT interrupt pin is connected to INT3 through the TSSR.

Figure 3-51. IFR0, IER0, DBIFR0, and DBIER0 Registers Layout

LEGEND: R = Read, W = Write, n = value at reset

Figure 3-52. IFR1, IER1, DBIFR1, and DBIER1 Registers Layout

3.17.2Interrupt Timing

The external interrupts (NMI and INT) are synchronized to the CPU by way of a two-flip-flop synchronizer. The interrupt inputs are sampled on falling edges of the CPU clock. A sequence on the interrupt pin of 1-0-0-0 on consecutive cycles is required for an interrupt to be detected. Therefore, the minimum low pulse duration on the external interrupts on the 5502 is three CPU clock periods.

TIM0, TIM1, WDTOUT, and HPI.HAS can be configured to generate interrupts to the CPU. When they are used for this function, these pins will generate the interrupt associated with that module, i.e., TIM0 will generate TINT0, HPI.HAS will generate DSPINT, etc. Three SYSCLK1 clock cycles must be allowed to pass between consecutive interrupts generated using the HPI.HAS signal; otherwise, the last interrupt will be ignored(i.e., a sequence of 0-1-1-1-0 on consecutive cycles is required for consecutive interrupts). For more information on configuring TIM0, TIM1, WDTOUT, and HPI.HAS as interrupt pins, please refer to the TMS320VC5501/5502 DSP Timers Reference Guide (literature number SPRU618) for the timer pins and to the TMS320VC5501/5502 DSP Host Port Interface (HPI) Reference Guide (literature number SPRU620) for the HPI pin.

3.17.3Interrupt Acknowledge

The IACK pin is used to indicate the receipt of an interrupt and that the program counter is fetching the interrupt vector location designated on the address bus. As the CPU fetches the first word or the software vector, it generates the IACK signal, which clears the appropriate interrupt flag bit. The IACK signal will go low for a total of one CPU clock pulse and then go high again. For maskable interrupts, note that the CPU will not jump to an interrupt service routine if the appropriate interrupt enable bit is not set; consequently, the IACK pin will not go low when the interrupt is generated.