TMS320VC5502
Fixed-Point Digital Signal Processor
www.ti.com
SPRS166J –APRIL 2001 –REVISED AUGUST 2006
3.13 External Bus Control Register
The External Bus Control Register is used to disable/enable the bus pullups, pulldowns, and bus holders of the 5502 pins. Table 3-46 lists which 5502 pins have pullups, pulldowns, and bus holders, and which bit on the XBCR enables/disables that feature. Please note that for pins with dual functionality (e.g., HC0, HC1, C0, etc.), the bus holder, pullup, and pulldown feature of each pin can be enabled or disabled regardless of the function of the pin at the time.
Table 3-46. Pins With Pullups, Pulldowns, and Bus Holders
XBCR CONTROL BIT |
PIN |
FEATURE |
|
|
TCK |
Pullup |
|
TEST |
TDI |
Pullup |
|
TMS |
Pullup |
||
|
|||
|
TRST |
Pulldown |
|
EMU |
EMU1/OFF |
Pullup |
|
EMU0 |
Pullup |
||
|
|||
WDT |
NMI/WDTOUT |
Pullup |
|
|
HC0 |
Pullup |
|
|
HC1 |
Pulldown |
|
|
HCNTL0 |
Pullup |
|
|
HCNTL1 |
Pullup |
|
HC |
HCS |
Pullup |
|
HR/W |
Pullup |
||
|
|||
|
HDS1 |
Pullup |
|
|
HDS2 |
Pullup |
|
|
HRDY |
Pullup |
|
|
HINT |
Pullup |
|
HD |
HD[7:0] |
Bus Holder |
|
|
C0 |
Bus Holder |
|
|
C1 |
Bus Holder |
|
|
C2 |
Bus Holder |
|
|
C3 |
Pullup |
|
|
C4 |
Bus Holder |
|
|
C5 |
Bus Holder |
|
|
C6 |
Bus Holder |
|
PC |
C7 |
Bus Holder |
|
C8 |
Bus Holder |
||
|
|||
|
C9 |
Bus Holder |
|
|
C10 |
Bus Holder |
|
|
C11 |
Bus Holder |
|
|
C12 |
Bus Holder |
|
|
C13 |
Bus Holder |
|
|
C14 |
Pullup |
|
|
C15 |
Bus Holder |
|
PD |
D[31:0] |
Bus Holder |
|
PA |
A[21:2] |
Bus Holder |
96 |
Functional Overview |
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TMS320VC5502
Fixed-Point Digital Signal Processor
www.ti.com
SPRS166J –APRIL 2001 –REVISED AUGUST 2006
3.13.1External Bus Control Register (XBCR)
15 |
|
|
|
|
|
|
8 |
|
|
|
|
Reserved |
|
|
|
|
|
|
R, 00000000 |
|
|
|
|
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
EMU |
TEST |
WDT |
HC |
HD |
PC |
PD |
PA |
R/W, 0 |
R/W, 0 |
R/W, 0 |
R/W, 0 |
R/W, 0 |
R/W, 0 |
R/W, 0 |
R/W, 0 |
LEGEND: R = Read, W = Write, n = value at reset |
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|||
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Figure 3-43. External Bus Control Register Layout (0x8800) |
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Table 3-47. External Bus Control Register Bit Field Description |
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BIT NAME |
BIT NO. |
ACCESS |
RESET VALUE |
|
DESCRIPTION |
|
|
Reserved |
15-8 |
R |
00000000 |
Reserved |
|
|
|
EMU |
7 |
R/W |
0 |
EMU bit |
|
|
|
|
|
|
|
∙ EMU = 0: Pullups on EMU1 and EMU0 pins are enabled. |
|||
|
|
|
|
∙ EMU = 1: Pullups on EMU1 and EMU0 pins are disabled. |
|||
TEST |
6 |
R/W |
0 |
TEST bit |
|
|
|
∙TEST = 0: Pullups/pulldowns on test pins are enabled (does not include EMU1 and EMU0 pins)
∙TEST = 1: Pullups/pulldowns on test pins are disabled (does not include EMU1 and EMU0 pins)
WDT |
5 |
R/W |
0 |
WDT bit |
|
|
|
|
∙ WDT = 0: Pullup on NMI/WDTOUT pin is enabled |
|
|
|
|
∙ WDT = 1: Pullup on NMI/WDTOUT pin is disabled |
HC |
4 |
R/W |
0 |
HPI control signal bit |
|
|
|
|
∙ HC = 0: Pullups/pulldowns on HPI control pins (HC0 and HC1) are |
|
|
|
|
enabled |
|
|
|
|
∙ HC = 1: Pullups/pulldowns on HPI control pins (HC0 and HC1) are |
|
|
|
|
disabled |
HD |
3 |
R/W |
0 |
HPI data bus bit |
|
|
|
|
∙ HD = 0: Bus holders on HPI data bus (pins HD[7:0]) are enabled |
|
|
|
|
∙ HD = 1: Bus holders on HPI data bus (pins HD[7:0]) are disabled |
PC |
2 |
R/W |
0 |
EMIF control signals |
|
|
|
|
∙ PC = 0: Bus holders and pullups on EMIF control pins are enabled |
|
|
|
|
∙ PC = 1: Bus holders and pullups on EMIF control pins are disabled |
PD |
1 |
R/W |
0 |
EMIF data bus signals |
|
|
|
|
∙ PD = 0: Bus holders on EMIF data bus (pins D[31:0]) are enabled |
|
|
|
|
∙ PD = 1: Bus holders on EMIF data bus (pins D[31:0]) are disabled |
PA |
0 |
R/W |
0 |
EMIF address bus signals |
|
|
|
|
∙ PA = 0: Bus holders on EMIF address bus (pins A[21:2]) are |
|
|
|
|
enabled |
∙ PA = 1: Bus holders on EMIF address bus (pins A[21:2]) are disabled
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Functional Overview |
97 |