TMS320VC5502

Fixed-Point Digital Signal Processor

www.ti.com

SPRS166J –APRIL 2001 –REVISED AUGUST 2006

3.10.6Reset Sequence

When RESET is low, the clock generator is in bypass mode with the input clock set to CLKIN or X2/CLKIN, dependent upon the state of GPIO4. After the RESET pin transitions from low to high, the following events will occur in the order listed below.

∙GPIO6 and GPIO7 are sampled on the rising edge of the reset signal. The state of GPIO6 and GPIO7 determines the function of the multiplexed pins of the 5502, see Section 3.3, Configurable External Ports and Signals, for more information on pin multiplexing. The state of GPIO6 and GPIO7 during the rising edge of reset determines the values for the Parallel/Host Port Mux Mode and the Serial Port 2 Mux Mode bits, respectively, of the External Bus Control Register (XBSR).

∙GPIO4 is sampled on the rising edge of the reset signal to set the state of the CLKMD0 bit of the Clock Mode Control Register (CLKMD), which in turns, determines the clock source for the DSP. The CLKMD0 bit selects either the internal oscillator output (OSCOUT) or the X2/CLKIN pin as the input clock source for the DSP. If GPIO4 is low at reset, the CLKMD0 bit will be set to 0 and the internal oscillator and the external crystal generate the input clock for the DSP. If GPIO4 is high, the CLKMD0 bit will be set to 1 and the input clock will be taken directly from the X2/CLKIN pin.

∙After the reset signal transitions from low to high, the DSP will not be taken out of reset immediately. Instead, an internal counter will count 41032 clock cycles to allow the internal oscillator to stabilize (only if GPIO4 was low). The internal counter will also add 70 reference clock cycles to allow the reset signal to propagate through different parts of the device.

∙After all internal delay cycles have expired, the IACK pin will go low for two CPU clock cycles to indicate this internal reset signal has been deasserted. The BOOTM[2:0] pins will be sampled and their values will be stored in the Boot Mode Register (BOOTM_MODE). The value in the BOOTM_MODE register will be used by the bootloader to determine the boot mode of the DSP.

∙Program flow will commence after all internal delay cycles have expired.

The 5502 has internal circuitry that will count down 70 reference clock cycles to allow reset signals to propagate correctly to all parts of the device after reset (RESET pin goes high). Furthermore, the 5502 also has internal circuitry that will count down 41,032 reference clock cycles to allow the oscillator input to become stable after waking up from power-down state or reset. If a reset is asserted, program flow will start after all stabilization periods have expired; this includes the oscillator stabilization period only if GPIO4 is low at reset. If the oscillator is coming out of power-down mode, program flow will start immediately after the oscillator stabilization period has completed. Table 3-24 summarizes the number of reference clock cycles needed before program flow begins.

Table 3-24. Number of Reference Clock Cycles Needed Until Program Flow Begins

All output (O/Z) and input/output (I/O/Z) pins (except for CLKOUT, ECLKOUT2, and XF) will go into high-impedance mode during reset and will come out of high-impedance mode when the stabilization periods have expired. All output (O/Z) and input/output (I/O/Z) pins will retain their value when the device enters a power-down mode such as IDLE3 mode.

3.11 Idle Control

The Idle function is implemented for low power consumption. The Idle function achieves low power consumption by gating the clock to unused parts of the chip, and/or setting the clock generator (PLL) and the internal oscillator to a power-down mode.

TMS320VC5502

Fixed-Point Digital Signal Processor

www.ti.com

SPRS166J –APRIL 2001 –REVISED AUGUST 2006

3.11.1Clock Domains

The 5502 provides six clock domains to power-off the main clock to the portions of the device that are not being used. The six domains are:

∙CPU Domain

∙Master Port Domain (includes DMA and HPI modules)

∙ICACHE

∙Peripherals Domain

∙Clock Generator Domain

∙EMIF Domain

3.11.2IDLE Procedures

Before entering idle mode (executing the IDLE instruction), the user has first to determine which part of the system needs to be disabled and then program the Idle Control Register (ICR) accordingly. When the IDLE instruction is executed, the ICR will be copied into the Idle Status Register (ISTR). The different bits of the ISTR register will be propagated to disable the chosen domains. Special care has to be taken in programming the ICR as some IDLE domain combinations are not valid (for example: CPU on and clock generator off).

3.11.2.1 CPU Domain Idle Procedure

The 5502 CPU can be idled by executing the following procedure.

1.Write '1'to the CPUI bit (bit 0 of ICR).

2.Execute the IDLE instruction.

3.CPU will go to idle state

3.11.2.2Master Port Domain (DMA/HPI) Idle Procedure

The clock to the DMA module and/or the HPI module will be stopped when the DMA and/or the HPI bit in the MICR is set to 1 and the MPIS bit in the ISTR becomes 1. The DMA will go into idle immediately if there is no data transfer taking place. If there is a data transfer taking place, then it will finish the current transfer and then go into idle. The HPI will go into idle regardless of whether or not there is a data transfer taking place. Software must confirm that the HPI has no activity before setting it to idle.

The 5502 DMA module and the HPI module can be disabled by executing the following procedure.

1.Write '1'to the DMA bit and/or the HPI bit in MICR.

2.Write '1'to the MPI bit in ICR.

3.Execute the IDLE instruction.

4.DMA and/or HPI go/goes to idle.

3.11.2.3Peripheral Modules Idle Procedure

The clock to the modules included in the Peripherals Domain will be stopped when their corresponding bit in the PICR is set to 1 and the PERIS bit in the ISTR becomes 1. Each module in this domain will go into idle immediately if it has no activity. If the module being set to idle has activity, it will wait until the activity completes before going into idle.

Each peripheral module can be idled by executing the following procedure.

1.Write '1'to the corresponding bit in PICR for each peripheral to be idled.

2.Write '1'to the PERI bit in ICR.

3.Execute the IDLE instruction.

4.Every peripheral with its corresponding PICR bit set will go to idle.

TMS320VC5502

Fixed-Point Digital Signal Processor

www.ti.com

SPRS166J –APRIL 2001 –REVISED AUGUST 2006

3.11.2.4 EMIF Module Idle Procedure

The 5502 EMIF can be idled in one of two ways: through the ICR and through the PICR. The EMIF will go into idle immediately if there is no data transfer taking place within the DMA. If there is a data transfer taking place, then the EMIF will wait until the DMA finishes the current transfer and goes into idle before going into idle itself. Please note that while the EMIF is in idle, the SDRAM refresh function of the EMIF will not be available.

The 5502 EMIF can be idled through the ICR only when the following modules are set to idle: CPU, I-Port, ICACHE, DMA, and HPI. To place the EMIF in idle using the ICR, execute the following procedure:

1.Write '1'to the DMA and HPI bits in MICR.

2.Write '1'to the CPUI, MPI, ICACHEI, EMIFI, and IPORTI bits in ICR.

3.Execute the IDLE instruction.

4.EMIF and all modules listed in Step 2 will go to idle.

The 5502 EMIF can also be idled through the PICR. To place the EMIF in idle using the PICR, execute the following procedure:

1.Write a '1'to the EMIF bit in PICR.

2.Write a '1'to the PERI bit in ICR.

3.Execute IDLE instruction.

4.EMIF will go to IDLE.

3.11.2.5IDLE2 Mode

In IDLE2 mode, all modules except the CLOCK module are set to idle state. To place the 5502 in IDLE2 mode, perform the following steps.

1.Write a '1'to all peripheral module bits in the PICR.

2.Write a '1'to the HPI and DMA bits in MICR.

3.Write a '1'to all domain bits in the ICR except the CLOCK domain bit (CLKI).

4.Execute the IDLE instruction.

5.All internal clocks will be disabled, the CLOCK module will remain active.

3.11.2.6IDLE3 Mode

In IDLE3 mode, all modules (including the CLOCK module) are set to idle state. To place the 5502 in IDLE3 mode, perform the following steps.

1.Clear (i.e., set to '0')the PLLEN bit in PLLCSR to place the PLL in bypass mode.

2.Set the PLLPWRDN and PLLRST bits in PLLCSR to '1'.

3.Write a '1'to all peripheral module bits in PICR (write 0x3FFF to PICR).

4.Write a '1'to the HPI and DMA bits in MICR (write 0x0003 to MICR).

5.Write a '1'to all domain bits and bit 9 in the ICR (write 0x03FF to ICR).

6.Execute the IDLE instruction.

7.PLL core is set to power-down mode and all internal clocks are disabled.

3.11.2.7IDLE3 Mode With Internal Oscillator Disabled

In this state, all modules (including the CLOCK module) are set to the idle state and the internal oscillator is set to the power-down mode. This is the lowest power-consuming state that 5502 can be placed under.

1.Clear (i.e., set to '0')the PLLEN bit in PLLCSR to place the PLL in bypass mode.

2.Set the PLLPWRDN, PLLRST, and OSCPWRDN bits in PLLCSR to '1'.

3.Set the WKEN register to specify which event will wake up internal oscillator [e.g., set bit 1 to have interrupt 0 (INT0) wake up the oscillator]. (1)

(1)Maskable external interrupts must be enabled through IER prior to setting the 5502 to IDLE.