TMS320VC5502

Fixed-Point Digital Signal Processor

www.ti.com

SPRS166J –APRIL 2001 –REVISED AUGUST 2006

3.9Direct Memory Access (DMA) Controller

The 5502 DMA provides the following features:

∙Four standard ports for the following data resources: two for DARAM, one for Peripherals, and one for External Memory

∙Six channels, which allow the DMA controller to track the context of six independent DMA channels

∙Programmable low/high priority for each DMA channel

∙One interrupt for each DMA channel

∙Event synchronization. DMA transfers in each channel can be dependent on the occurrence of selected events.

∙Programmable address modification for source and destination addresses

∙Idle mode that allows the DMA controller to be placed in a low-power (idle) state under software control

The 5502 has an Auto-wakeup/Idle function for McBSP to DMA to on-chip memory data transfers when the DMA and the McBSP are both set to IDLE. In the case that the McBSP is set to external clock mode and the McBSP and the DMA are set to idle, the McBSP and the DMA can wake up from IDLE state automatically if the McBSP gets a new data transfer. The McBSP and the DMA enter the idle state automatically after data transfer is complete. [The clock generator (PLL) should be active and the PLL core should not be in power-down mode for the Auto-wakeup/Idle function to work.]

The 5502 DMA controller allows transfers to be synchronized to selected events. The 5502 supports 16 separate synchronization events and each channel can be tied to separate synchronization event independent of the other channels. Synchronization events are selected by programming the SYNC field in the channel-specific DMA Channel Control Register (DMA_CCR).

The 5502 DMA can access all the internal DARAM space as well as all external memory space. The 5502 DMA also has access to the registers for the following peripheral modules: McBSP, UART, GPIO, PGPIO, and I2C.

3.9.1DMA Channel 0 Control Register (DMA_CCR0)

The DMA Channel 0 Control Register (DMA_CCR0) bit layouts are shown in Figure 3-11. DMA_CCR1 to DMA_CCR5 have similar bit layouts. See the TMS320VC5501/5502 DSP Direct Memory Access (DMA) Controller Reference Guide (literature number SPRU613) for more information on the DMA Channel n Control Register (n = 0, 1, 2, 3, 4, or 5).

LEGEND: R = Read, W = Write, n = value at reset

Figure 3-11. DMA Channel 0 Control Register Layout (0x0C01)

The SYNC field (bits[4:0]) of the DMA_CCR register specifies the event that can initiate the DMA transfer for the corresponding DMA channel. The five bits allow several configurations as listed in Table 3-9. The bits are set to zero upon reset. For those synchronization modes with more than one peripheral listed, the Serial Port 2 Mux Mode bit field of the External Bus Selection Register (XBSR) dictates which peripheral event is actually connected to the DMA input.

TMS320VC5502

Fixed-Point Digital Signal Processor

www.ti.com

SPRS166J –APRIL 2001 –REVISED AUGUST 2006