3.5Timers

TMS320VC5502

Fixed-Point Digital Signal Processor

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SPRS166J –APRIL 2001 –REVISED AUGUST 2006

Each timer has one input, one output, and one interrupt signal: TIN, TOUT, and TINT, respectively. Timer 0, Timer 1, and the Watchdog Timer are each assigned a pin: TIM0 pin is assigned to Timer 0, TIM1 is assigned to Timer 1, and NMI/WDTOUT is used by the Watchdog Timer. The input (TIN) or output (TOUT) signal of Timer 0, Timer 1, and the Watchdog Timer can be connected to their respective pins via the Timer Signal Selection Register (TSSR).

The DSP/BIOS timer input, output, and interrupt signals are not internally connected. No interrupts are needed from this timer; therefore, the timer interrupt signal is not internally connected to the CPU interrupt logic.

The interrupt signal (TINT) of the Watchdog Timer can be internally connected to the NMI, RESET, and INT3 signals via the TSSR.

Note that the NMI/WDTOUT pin has a dual function: Watchdog Timer pin and NMI input pin. The function of the NMI/WDTOUT pin can be selected through the TSSR.

For more information on the 5502 timers, see the TMS320VC5501/5502 DSP Timers Reference Guide (literature number SPRU618).

3.5.1Timer Interrupts

As stated earlier, each timer has one input, one output, and one interrupt signal: TIN, TOUT, and TINT, respectively. The interrupt signals of Timer 0 and Timer 1 are directly connected to the interrupt logic of the DSP (see Figure 3-6). The interrupts for Timer 0 and Timer 1 are maskable and can be enabled or disabled through the TINT0 and TINT1 bits of the interrupt enable registers (IER0 and IER1); setting TINT0 of IER0 to '1'enables the interrupt for Timer 0 and setting TINT1 of IER1 enables the interrupt for Timer 1.

TMS320VC5502 DSP

Interrupt Logic

Figure 3-6. Timer Interrupts

TMS320VC5502

Fixed-Point Digital Signal Processor

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SPRS166J –APRIL 2001 –REVISED AUGUST 2006

The interrupt signal for the Watchdog Timer can be internally connected to the RESET, INT3, or NMI signals by setting the IWCON bit of the Timer Signal Selection Register (TSSR) appropriately (see Figure 3-6). The DSP will be reset once the Watchdog Timer generates an interrupt if the timer interrupt is connected to RESET (IWCON = '01')A. non-maskable interrupt will be generated if the timer interrupt is connected to NMI (IWCON = '10')An. external interrupt will be generated when the timer interrupt signal is connected to INT3 (IWCON = '11'),but only if the INT3 bit of IER0 is set to '1'.

Refer to Section 3.17, Interrupts, for more information on using interrupts.

3.5.2Timer Pins

The 5502 has one pin for each timer: TIM0 for Timer 0, TIM1 for Timer 1, and NMI/WDTOUT for the Watchdog Timer. Either the output (TOUT) or input (TIN) signal can be connected to the timer pin (see Figure 3-7). When the timer pin is configured as an output, the TOUT signal is connected to the pin. The TIN signal is connected to the pin when the pin is configured as an input. Each pin can be configured as input or output through the Timer Signal Selection Register (TSSR) (bits TIM0_MODE, TIM1_MODE, and WDT_MODE).

Figure 3-7. Timer Pins

When configured as input, the timer pin can be used to source an external clock to the timer. Also, when the timer pin is configured as input and the timer is running off an internal clock, the timer pin can be used to start or stop count of the timer (clock gating).

When the timer pin is configured as an output, the timer pin can signal a pulse (pulse mode) or a change of state (clock mode) when the timer count matches its period.

The NMI/WDTOUT pin has two functions: Watchdog Timer pin or NMI pin. The NMI/WDTOUT_CFG bit of the TSSR controls the function of this pin. It is possible to configure the NMI/WDTOUT pin as NMI (NMI/WDTOUT_CFG = '1')and also connect the Watchdog Timer TINT signal to the NMI signal (IWCON = '10')In. this case, the external NMI signal will be overridden by the TINT signal of the Watchdog Timer, i.e., applying a signal to the NMI/WDTOUT pin will not generate the non-maskable interrupt NMI.

TMS320VC5502

Fixed-Point Digital Signal Processor

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SPRS166J –APRIL 2001 –REVISED AUGUST 2006

For all three timers (Timer 0, Timer 1, and the Watchdog Timer), both the TIN and TOUT signals can be used for general-purpose input/output. The timer pin must be configured for input to use the TIN signal as general-purpose input/output. The timer pin can be configured as an input by setting the pin mode bit of the Timer Signal Selection Register (TSSR) to '0'The. TOUT signal can be used as general-purpose input/output if the timer pin is configured for output. The timer pin can be configured as an output by setting the pin mode bit of the TSSR to '1'The. GPIO Enable Register (GPEN), GPIO Direction Register (GPIODIR), and the GPIO Data Register (GPDAT) of each timer can be used to control the state of the timer pins when used as general-purpose input/output.

3.5.3Timer Signal Selection Register (TSSR)

The Timer Signal Selection Register (TSSR) controls several pin characteristics for Timer 0, Timer 1, and the Watchdog Timer. The TSSR can be used to specify whether the pins of Timer 0, Timer 1, and the Watchdog Timer are inputs or outputs. The TSSR also determines how the interrupt signal of the Watchdog Timer is connected internally and sets the function for the NMI/WDTOUT pin of the 5502. By default, all timer pins (TIM0, TIM1, and NMI/WDTOUT) are set as inputs, the interrupt signal of the Watchdog Timer is not internally connected to anything, and the NMI/WDTOUT pin has the function of the NMI signal.