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AT45DB321
Detailed Bit-level Read Timing – Inactive Clock Polarity Low
Main Memory Page Read
CS |
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SCK |
1 |
2 |
3 |
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4 |
5 |
60 |
61 |
62 |
63 |
64 |
65 |
66 |
67 |
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tSU |
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COMMAND OPCODE |
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SI |
0 |
1 |
0 |
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1 |
0 |
X |
X |
X |
X |
X |
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tV |
DATA OUT |
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HIGH-IMPEDANCE |
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SO |
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D7 |
D6 |
D5 |
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MSB |
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Buffer Read |
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CS |
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SCK |
1 |
2 |
3 |
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4 |
5 |
36 |
37 |
38 |
39 |
40 |
41 |
42 |
43 |
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tSU |
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COMMAND OPCODE |
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SI |
0 |
1 |
0 |
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1 |
0 |
X |
X |
X |
X |
X |
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tV |
DATA OUT |
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HIGH-IMPEDANCE |
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SO |
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D7 |
D6 |
D5 |
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MSB |
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Status Register Read |
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CS |
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SCK |
1 |
2 |
3 |
4 |
5 |
6 |
7 |
8 |
9 |
10 |
11 |
12 |
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16 |
17 |
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tSU |
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COMMAND OPCODE |
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SI |
0 |
1 |
0 |
1 |
0 |
1 |
1 |
1 |
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tV |
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STATUS REGISTER OUTPUT |
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HIGH-IMPEDANCE |
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SO |
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D7 |
D6 |
D5 |
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D1 |
D0 |
D7 |
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MSB |
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LSB |
MSB |
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