Allen and Holberg - CMOS Analog Circuit Design
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Allen and Holberg - CMOS Analog Circuit Design |
Page III.2-1 |
INTRINSIC CAPACITORS OF THE MOSFET
Types of MOS Capacitors
1.Depletion capacitance (CBD and CBS)
2.Gate capacitances (CGS, CGD, and CGB)
SiO2
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Drain |
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C1 |
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C2 |
C3 |
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C4 |
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C |
BS |
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CBD |
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Bulk
Figure 3.2-4 Large-signal, charge-storage capacitors of the MOS device.
Allen and Holberg - CMOS Analog Circuit Design |
Page III.2-2 |
Depletion Capacitors
Bulk-drain pn junction -
CBD
Capacitance approximation for strong forward bias
CBD0xArea
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(FC) |
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B |
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VBD |
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Forward |
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φB |
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Reverse Bias |
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Bias |
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CBD0 ABD |
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CBS0 ABS |
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CBD = |
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vBD MJ |
andCBS = |
vBS MJ |
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− |
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1 |
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1 − |
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φ B |
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B |
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where,
ABD (ABS) = area of the bulk-drain (bulk-source)
φΒ = bulk junction potential (barrier potential)
MJ = bulk junction grading coefficient ( 0.33 ≤ MJ ≤ 0.5)
For strong forward bias, approximate the behavior by the tangent to the above CBD or CBS curve at vBD or vBS equal to (FC)·φ B.
CBD = |
CBD0ABD |
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vBD |
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vBD > (FC)·φ B |
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− (1+MJ)FC + FC |
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(1+FC)1+MJ |
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φB |
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and |
CBS0ABS |
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vBS |
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CBD = |
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vBS > (FC)·φ B |
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− (1+MJ)FC + FC |
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(1+FC)1+MJ |
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φB |
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Allen and Holberg - CMOS Analog Circuit Design |
Page III.2-3 |
Bottom & Sidewall Approximations
Polysilicon gate |
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H |
G |
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D |
C |
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Source |
Drain |
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F |
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E |
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A |
B |
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SiO2 |
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Bulk |
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Drain bottom = ABCD
Drain sidewall = ABFE + BCGF + DCGH + ADHE
CBX =
and
CBX =
vBX ≥
where
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(CJ)(AX) |
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(CJSW)(PX) |
, vBX ≤ (FC)(PB) |
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v |
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v |
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− |
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BX MJ |
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BX MJSW |
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PB |
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PB |
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(CJ)(AX) |
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v |
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− (1 + MJ)FC + MJ |
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BX |
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(1 − FC)1+MJ |
1 |
PB |
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(CJSW)(PX) |
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vBX |
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(1 − FC)1+MJSW |
1 |
− (1 + MJSW)FC + PB |
(MJSW) , |
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(FC)(PB)
AX = area of the source (X = S) or drain (X = D)
PX = perimeter of the source (X = S) or drain (X = D) CJSW = zero-bias, bulk-source/drain sidewall capacitance MJSW = bulk-source/drain sidewall grading coefficient
Allen and Holberg - CMOS Analog Circuit Design |
Page III.2-4 |
Overlap Capacitance
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Mask L |
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Oxide encroachment |
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Actual |
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L (Leff) |
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Mask |
Actual |
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W (Weff) |
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LD |
W |
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Gate
Source-gate overlap |
Drain-gate overlap |
capacitance CGS (C1) |
capacitance CGD (C3) |
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Gate |
FOX |
FOX |
Source |
Drain |
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Bulk |
C1 = C3 (LD)(Weff)Cox = (CGXO)Weff
Allen and Holberg - CMOS Analog Circuit Design |
Page III.2-5 |
Gate to Bulk Overlap Capacitance
Overlap |
Overlap |
C5 |
Gate |
C5 |
FOX |
FOX |
Source/Drain |
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Bulk |
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On a per-transistor basis, this is generally quite small
Channel Capacitance
C2 = Weff(L − 2LD)Cox = Weff(Leff)Cox
Drain and source portions depend upon operating condition of transistor.
Allen and Holberg - CMOS Analog Circuit Design |
Page III.2-6 |
MOSFET Gate Capacitance Summary:
Capacitance |
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C2 + 2C5 |
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C |
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C |
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2 |
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GS |
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1 |
_ C |
2 |
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3 |
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C |
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1 |
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C |
GS |
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GD |
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_ C |
2 |
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2 |
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vDS = constant |
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CGS, CGD |
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CGD |
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vBS = 0 |
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C1, C3 |
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CGB |
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2C5 |
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0 |
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Off |
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Saturation |
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Non- |
vGS |
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VT |
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vDS +VT |
Saturation |
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iD
vDS = vGS - VT
Non-Sat
Region
Saturation
Region
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Cutoff Region |
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0.5 |
1.0 |
1.5 |
2.0 |
2.5 |
0 |
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vDS = |
constant |
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Allen and Holberg - CMOS Analog Circuit Design |
Page III.2-7 |
CGS, CGD, and CGB
Off
CGB = C2 + 2C5 = Cox(Weff)(Leff) + CGBO(Leff)
CGS = C1 Cox(LD)(Weff) = CGSO(Weff)
CGD = C3 Cox(LD)(Weff) = CGDO(Weff)
Saturation
CGB = 2C5 = CGBO (Leff)
CGS = C1 + (2/3)C2 = Cox(LD + 0.67Leff)(Weff)
= CGSO(Weff) + 0.67Cox(Weff)(Leff)
CGD = C3 Cox(LD)(Weff) = CGDO(Weff)
Nonsaturated
CGB = 2C5 = CGBO (Leff)
CGS = C1 + 0.5C2 = Cox(LD + 0.5Leff)(Weff)
= (CGSO + 0.5CoxLeff)Weff
CGD = C3 + 0.5C2 = Cox(LD + 0.5Leff)(Weff)
= (CGDO + 0.5CoxLeff)Weff
Allen and Holberg - CMOS Analog Circuit Design
Small-Signal Model for the MOS Transistor
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D |
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rD |
Cbd |
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inrD |
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Cgd |
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gmvgs |
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gds |
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gbd |
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G |
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inD |
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Cgs |
g |
v |
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g |
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mbs |
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inrS |
C |
bs |
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Cgb |
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r |
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Figure 3.3-1 Small-signal model of the MOS transistor.
gbd = ∂IBD (at the quiescent point) 0
∂VBD
and
gbs = ∂IBS (at the quiescent point) 0
∂VBS
The channel conductances, gm, gmbs, and gds are defined as
gm = ∂ID (at the quiescent point)
∂VGS
gmbs = ∂∂VIDBS (at the quiescent point)
and
g = ∂ID (at the quiescent point) ds ∂VDS
Page III.3-1
B
Allen and Holberg - CMOS Analog Circuit Design |
Page III.3-2 |
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Saturation Region |
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gm = |
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(2K'W/L)| ID|(1 + λ VDS) (2K'W/L)|ID| |
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= |
−∂I |
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∂V |
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g |
mbs |
∂V |
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= − |
D |
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SB |
∂V |
∂V |
SB |
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Noting that |
∂ID = |
−∂ID , we get |
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∂VT |
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∂VGS |
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γ |
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gmbs = gm 2(2|φF| + VSB)1/2 = η gm |
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gds = go = |
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ID λ |
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ID |
λ |
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1 + λ VDS |
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Relationships of the Small Signal Model Parameters upon the DC Values of Voltage and Current in the Saturation Region.
Small Signal |
DC Current |
DC Current and |
DC Voltage |
Model Parameters |
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Voltage |
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gm |
(2K' IDW/L)1/2 |
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2K' W(VGS -VT) |
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L |
gmbs |
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γ (2IDβ)1/2 |
γ ( β (VGS −VT) ) |
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2(2|φF | +VSB) 1/2 |
2(2|φF | + VSB)1/2 |
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gds |
λ ID |
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Allen and Holberg - CMOS Analog Circuit Design |
Page III.3-3 |
Nonsaturation region
gm = ∂Id = β VDS
∂VGS
gmbs = |
∂ID |
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βγVDS |
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2(2|φF | + VSB)1/2 |
and
gds = β(VGS − VT − VDS)
Relationships of the Small-Signal Model Parameters upon the DC Values of Voltage and Current in the Nonsaturation Region.
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Small Signal |
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DC Voltage and/or Current |
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Model Parameters |
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Dependence |
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gm |
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= β VDS |
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gmbs |
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β γ VDS |
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2(2|φF | +VSB)1/2 |
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gds |
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= β (VGS −VT −VDS) |
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Noise |
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4kT |
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(A2) |
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i nrD = |
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rD |
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f |
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4kT |
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i nrS = |
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f |
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rS |
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and |
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i nD2 = |
8kT g |
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(1+η) |
(KF )I |
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m |
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f (A2) |
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f Cox L2 |
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