Camenzind_Analog design chips

11 Timers and Oscillators

Summer of 1970. The economy was at the bottom of the cycle and Signetics, the promising young company I had joined just two years before, laid off half of its employees.

Disgusted with the turn of events, I decided it was time to strike out on my own and rented space between two Chinese restaurants in downtown Sunnyvale, California. Signetics (now Philips) lent me the equipment I needed and gave me a one-year contract to develop a new IC.

The idea for the new IC came from the work I did at Signetics on the phase-locked loop. I had needed an oscillator whose frequency could be set by an external resistor and a capacitor and was not affected by changes in either supply voltage or temperature. Several products resulted from the basic design, among them the NE566 Voltage-Controlled Oscillator.

resistor becomes (1/6*Vcc)/Rext.

Depending on the state of the switch

controlled by the flip-flop, the external capacitor is either charged with the current, or discharged with a current of the same magnitude through a 1:1 current mirror.

There is a divider with three identical resistors, producing 1/3 Vcc and 2/3 Vcc at the two taps. Two comparators, referenced to these taps, watch the voltage across the external capacitor. If it moves above 2/3 Vcc, comparator 1 sets the flip-flop, the switch diverts the current to the mirror and the capacitor is discharged. When the voltage across the capacitor reaches 1/3 Vcc, comparator 2 resets the flip flop and the capacitor is charged again.

This endless cycle

3 R C

What I proposed to Signetics was this circuit, modified so it could also be triggered and produce a single cycle only, i.e. it would be both an oscillator and a timer.

The project almost didn't get off the ground; the engineering staff didn't think much of the idea. Timers at the time were put together from an op-amp or comparator and a few discrete components, including a Zener diode or two. They argued that such a design would cut into the sales of their present ICs. But the marketing manager, Art Fury, over-rode them; a man with immense practical experience, he simply had the gut feeling that such a timer would sell.

It was a one-year contract and designing the circuit took half of that. No computer analysis then, the circuit had to be laboriously breadboarded. When everything was working I wrote a development report and gave a design review at Signetics. The design passed without any comments.

But something wasn't quite right. I felt that I had missed something, that I could do better. It bothered me that the design required nine pins, which was about the most unfortunate number I could have picked. There was an 8-pin package; the next higher number was 14.

I started on the layout. In 1971 this meant sitting at a drawing board for several weeks, fitting devices together into the minimum rectangular shape and checking each dimension by hand. Then, about two weeks after the design review, on the way home after work, it suddenly hit me: what would happen if I got rid of the voltage-to-current converter and charged (and discharged) the capacitor directly with a resistor? That would bring the pin-count down to eight.

I made a U-turn, went back to work and tried it. Sure enough, the timing didn't change as I varied the supply voltage. It was my own limitation that had made me assume that only a linear relationship between charge current and end-voltage would cause the cancellation effect. Even though the charging of a capacitor through a resistor causes an exponential rise of the voltage, the cancellation was just as effective. In fact, having eliminated the voltage-to-current converter, I now had not only a smaller but also a more accurate circuit.

I made the changes in the circuit but didn't bother to request a second design review. I only told Art Fury, who was pleased; an 8-pin package was then significantly less expensive than a 14-pin one.

It took another five months to draw the layout, cut the patterns on Rubylith (by hand), spend endless hours hunched over a light-table to check dimensions and connections (again: by hand, no computers), make a mask and a prototype wafer and then evaluate the IC, which Art Fury decided to call the NE555.

In the meantime, one of my former colleagues left Signetics to join a start-up. The first circuit this start-up brought to market was the timer I had described in my design review. Time -wise they beat Signetics by two months, but when the real 555 came out, they had to withdraw their version very quickly.

The market reaction to the 555 timer was truly amazing. Art Fury made history by bringing out the circuit at an unprecedented low price, 75 cents. I had deliberately made the design flexible, but nine out of ten applications were in areas and ways I had never contemplated. For months I was inundated by phone calls from engineers who had a new idea for using the timer. To this day the 555 has been the best-selling IC every year, copied by numerous companies. Except for a CMOS version, the design has never been changed.

Looking at the design now, 33 years later, there are many areas where it can be improved with the design techniques we have learned since and with the enormous benefit of computer simulation. So, let's look at the actual 555 timer and then a version which benefits from 33 years of progress.

Fig. 11-3 The original 555 timer.

Both comparators use Darlington input stages. This makes the timer fairly slow, but allows an extreme range of external resistance. Comparator 1 consists of Q1 to Q8. The four PNP transistors form a current mirror with gain, provided by the unequal emitter resistors.

The output of this comparator feeds into a 4.7kOhm resistor (R11), which is part of the cross-connection in the flip-flop (Q16, Q17). Comparator 2 (Q10 to Q15) resets the flip-flop.

The output stage, which must be able to sink or source some 200mA, is controlled by Q20. In the high state the Darlington pair Q21/Q22 delivers the current, but at a cost of a voltage drop of about 2 Volts. In the low state Q24 receives sufficient base current to work alone up to about 50mA; beyond that, as the voltage drop increases, Q23 feeds extra current into the base circuit.

There are several flaws in this design, indicative of the early period of IC design (and the inexperience of a rookie designer). Neither comparator is well balanced, showing offsets of as much as 30mV. The circuit can get away with that because the voltage swing is quite large.

The operating currents are quite large; the lateral PNP transistors run at up to 1mA. That was acceptable at the time since the devices had 10um geometries; today it would be excessive.

The output stage consumes a considerable amount of current in the low state and, during switching, both output transistors are on for a brief period of time, producing a current spike in the supply.

In the timer connection the period starts with a negative-going trigger pulse, which resets the flip-flop through comparator 2 and moves the output high. When the voltage across C1 reaches 2/3 Vcc, comparator 1 sets the flip-flop, C1 is rapidly discharged and the output moves low. Despite the bad offset voltage the accuracy is quite remarkable: the error in timing is around 1% with a temperature coefficient of 24ppm/ oC. The timing formula is:

t = 11. R1 C1

In the oscillator connection there are two external resistors and the voltage across C1 moves between 1/3 Vcc and 2/3 Vcc with a frequency and duty cycle of:

It is not quite possible to achieve a 50% duty-cycle; charging and discharging the timing capacitor through a resistor connected to the output is not such a good idea; the high and low voltage drops are unequal and have significant temperature coefficients.

There is a CMOS version of the 555 (see below) and a redesign for operation from a single battery cell (see references), but the circuit is still being sold today in its original form, despite the fact that much better performance is possible with more modern design techniques. Here is my candidate: