Camenzind_Analog design chips

over temperature but with a Monte Carlo analysis (which varies the threshold voltages and transconductances).

Though rarely needed in an ASIC, the ideal comparator has a rail-to- rail input (it already has a rail-to-rail output).

Fig. 9-7: In CMOS ground level operation can be achieved with device dimensions.

This is actually quite easy to achieve: two input differential pairs, one n-channel, the other p-channel; mirror the currents of one and sum the result with the currents of the other.

In this example the active load of figure 9-4 was chosen, again with sufficient positive feedback to give a snap-action (M5-M8). Note that M5M8 and M9-M12 have a considerably large w/l ratio compared to the corresponding M1 - M2 and M3 - M4 to allow the input to go slightly beyond Vcc and ground.

Current Comparators

Q3, which is easily reduced by adding another NPN stage and using a more sophisticated current mirror in place of Q4.

have to make the input current mirrors quite large to get enough accuracy. Find out with a Monte Carlo analysis.

10 Transconductance Amplifiers

For a while it looked like there would be a second universal building block and the concept was called the Operational Transconductance Amplifier. But the OTA has rather severe limitations and there is no danger that it might de-throne the op-amp anytime soon.

Let's examine the concept using a simple bipolar design. Just like in an op-amp there is a differential input pair (Q1, Q2). Its collector currents are mirrored separately by Q3-Q5 and Q6-Q8. One of the mirrored currents

"little re") because it changes with emitter current. At Ie = 1mA it amounts to roughly 26 Ohms (at room temperature), at 100uA 260 Ohms, at 10uA 2.6kOhm, i.e. it is inversely proportional to Ie. (There is also a constant resistance in series with re, the physical resistance between the emitter contact and the base-emitter junction; this becomes significant at higher currents).

The transconductance of a bipolar transistor is simply:

g = 1

m re

Thus with an emitter current of 100uA the transconductance is (1/260) Ohms, i.e. a 1mV signal at the base cases a change in collector current of 3.8uA. In a differential stage the transconductance is half of that since there is an re in each transistor (and we double the total current so that each emitter receives 100uA).

In figure 10-1 the currents are mirrored in a ratio of 1:1 so that the collector currents of Q1 and Q2 appear unchanged at the output. With no signal at the input they cancel each other but, as one input is moved up or down, one current becomes larger and the other one smaller by the same amount. Thus the total transconductance is doubled and we have the same value as for a single transistor.

Without some DC resistance at the output a transconductance amplifier is really quite impractical. Even the slightest mismatch in any of the transistors would slam the output voltage into one of the supply rails; we need some impedance like Rload to keep this voltage near the center. Rload converts the current output into a voltage output, which means that we no longer have a transconductance amplifier but simply a voltage amplifier (with a high output impedance to boot). Very few of the OTAs are actually used as transconductance amplifiers.

With Rload back in the circuit the total voltage gain is now simply:

So we have an amplifier whose gain can be varied (over a wide range) by varying a current .

And herein lies the problem. The input signal also varies the current, and thus the gain changes with the amplitude of the signal. The result: distortion. With a small signal at the input this may be tolerable for some application, but not with a large signal. Here is the tally:

So, if you have to handle a signal greater than about 20mVp, this circuit is a poor choice. You cannot use feedback or emitter resistors (for Q1 and Q2) to linearize it, it would interfere with the variable gain.

There is another problem, not just for this circuit but for all such schemes: offset. A mismatch in not only the input stage but all three current mirrors will show up as an offset (and added distortion) at the output, increasing in magnitude as Igain increases. In this circuit this amounts to 60mV worst-case at 100uA. Also, remember that bipolar transistors have input currents.

There is help, though, and as usual you need to add a few more