Camenzind_Analog design chips

8 Operational Amplifiers

Op-amp design is a specialty, peopled by a small group of engineers forever dedicated to the quest of finding the universal building block. None has ever been found (hence the large number of different op-amps) but still they toil. Year after year they come up with small improvements; and each new design has one imperative requirement; it must work in any application without creating smoke or - heaven forbid - oscillation.

When designing an op-amp for an ASIC the precise application is known, so the circuit does not need to be universal and the task is easier. Not exactly a cinch, but nothing compared to what a designer of commercial op-amps has to face.

The majority of op-amps have three stages. The first stage converts the differential signal into a single-ended one; the second one provides the bulk on the gain and the third one the required output power. There is no law that says it has to be this way, it just turned out to be an approach that works well.

Bipolar Op-Amps

as a load the current sink Q8

Fig. 8-1: Simple 3-stage op-amp.

and the base current of Q5, thus

its gain is also limited only by those two. The output stage is a simple emitter follower with a pull-down current sink.

The operating currents for all three stages are derived from I1 through a multiple current mirror. Q9, with two emitters, delivers two times I1, an arbitrary choice; more emitters could be used if more current is required at the output for negative-going signals.

Q7 and Q8 are identical, which is no arbitrary choice. By making the collector currents of Q4 and Q3 (both halves) equal, Q3 takes as much base current from Q1 as Q4 does from Q2. Thus there is no designed-in base current error and the offset at the input is zero (for ideal matching).

Common Mode Range: Describes the minimum to maximum DC level at which the two inputs are functional. Desirable is rail-to-rail, i.e. from the negative supply to the positive one, but many op-amps only work with the inputs a volt or two above -V (or ground for a single supply) to some voltage below +V.

Common-Mode Rejection: If you connect both inputs together, bias them at a functional DC level and superimpose on the bias a small AC voltage, no signal should ideally appear at the output. In reality a small signal leaks through and the measure describes how much smaller this signal is (in dB) compared to the input.

The common-mode range in this design has limitations. The two inputs need a dc level of at least one VBE (Q1, Q2) plus a saturation voltage (Q7) above -V. If they move below this level the input pair gets no operating current. Also, the inputs need to be about 200mV below +V, otherwise Q1 or Q2 saturate and Q3 or Q4 are without current. At the output Q5 can pull the output only to within a VBE of +V.

There is also another flaw: being bases of bipolar transistors, the inputs need a current. With a minimum hFE of 100 and 50uA flowing per transistor, this amounts to base current of 0.5uA worst case. With a 100kOhm input resistance for one input and zero for the other this could amount to as much as a 50mV error at the output.

Frequency compensation is achieved with a single capacitor from the output to the high-impedance node at the output of the first stage. It

the AC signal. You want to choose the inductor and capacitor large enough so they have no effect at even the lowest frequency of interest for the circuit. Neither 1 million Henrys nor 1 Farad are practical values; they don't need to be.

And here is what we

adequate.

But, as pointed out in chapter 6, a phase-margin analysis is not the real test of stability. AC analysis uses

infinitely small signals (even if it says the signal is 1 Volt) and the operating currents and voltages are not disturbed. So, to be certain, we would have to repeat this analysis for the DC conditions over the entire (large-signal)

stable, there is no ringing, just a small overshoot.

But the curve shows something else: rise and fall-times are substantial and almost straight lines. This is the slew-rate, the time it takes to charge and discharge the 10pF capacitor over a 2-Volt span with the operating current. You can speed it up by increasing the operating current, at the cost of power consumption.

In doing this test we assume that the op-amp needs to be operated as a buffer. What if, in a specific application, the closed loop gain is never lower than 40dB? In such a case we only have an excess open-loop gain of about 45dB, which makes compensation considerably easier.

Let's examine this. In figure 8-6 we have the same circuit as in the loop gain analysis before, except that the feedback resistors are in the loop also.

oscillation). And, because the compensation capacitor is smaller, the slewrate is substantially higher.

No consideration has been given so far to noise and noise performance is in fact not that great in this design. The majority of the noise is created in the input stage; in subsequent stages the signal is larger

not require more the 50uA), but only down to about 1 Volt above the negative rail.

Let's now consider a design in which the inputs can be operated all the way down to the level of the negative rail and the output swings (almost) rail-to-rail. The input stage in figure 8-11 is a configuration known as the folded cascode stage . With an operating current (I1) of 10uA the voltage drop across R1 and R2 is a mere 50mV, thus the inputs can go about 250mV below the negative supply rail without saturating Q1 or Q2.

The collector currents of Q1 and Q2 upset the balance of the Wilson current mirror Q3, Q4 and Q5 and the difference signal is picked up by Q6.

voltage for the base

of Q11. If you follow the emitter base of Q11, Q12 and Q14, you notice there are also three diodes in series to the V- rail. Thus, as the input signal to the output stage moves up and down (by a few millivolts), the current in Q11 fluctuates. It is this current, amplified by the size ratio of Q13 to Q10 (here about 6) that becomes the pull-up portion at the output. Q7 to Q9 are deliberately made larger than Q11, Q12 and Q14 so that the idle current in the output is small. This creates a small "dead-band" (see chapter 16) but, because of the large loop gain the distortion is very small (0.0004% for a ± 4.7Vp signal at 1kHz).