Chapter 12: Intel 82350DT EISA Chipset

ISP interface unit

The ISP interface unit provides the interconnect between the EBC and the ISP chip. For a description of the signals involved, refer to the next section.

82357 Integrated System Peripheral (ISP)

Introduction

The majority of the logic contained within the Integrated System Peripheral, or ISP, was described in detail earlier in this publication and in the MindShare book entitled ISA System Architecture. The information presented here is intended as a summary of the functions present in the ISP. Where applicable, signals indigenous to the ISP are described. Figure 12-6 provides a detailed view of the major logic blocks contained within the ISP.

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Figure 12-6. The ISP Block Diagram

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Chapter 12: Intel 82350DT EISA Chipset

NMI Logic

In an EISA system, there are four possible hardware causes for generation of NMI to the host CPU:

•A Channel Check, or CHCHK#, from an ISA or EISA card reporting a catastrophic failure.

•A system board RAM parity error (PARITY#).

•A Watchdog Timer timeout because an applications program has disable interrupt recognition for an extended period of time.

•A bus Timeout from the Central Arbitration Control because the current bus master has refused to yield the buses within the allowed period of time (8 microseconds for an EISA bus master or 2.5 microseconds for a DMA channel).

The programmer may also force the NMI logic to generate an NMI by writing to I/O port 0462h with any data.

Interrupt Controllers

The ISP contains two modified Intel 8259A Programmable Interrupt Controllers in a master/slave configuration. Together, they provide a total of fifteen interrupt request lines. Eleven of these are attached to the EISA/ISA card slots, while the remainder are reserved for special system board functions. The Interrupt Acknowledge input to the ISP is conspicuous by its absence. When a bus master other than the DMAC or the Refresh logic is bus master, the ST2 signal line is an input to the ISP and it performs the interrupt acknowledge function. Whenever the EBC detects an interrupt acknowledge bus cycle on the host bus, it sets ST2 low to signal interrupt acknowledge to the interrupt controllers in the ISP.

Two new registers have been added to allow individual programming of each interrupt request input as level-sensitive or edge-triggered. They are referred to as the ELCR, or Edge/Level Control registers. The master interrupt controller's ELCR resides at I/O port 04D0h, while the slave's resides at I/O port 04D1h. Bit zero in the master's ELCR corresponds to the IRQ0 input, while bit seven corresponds to the IRQ7 input. Bit zero in the slave's ELCR corresponds to the IRQ8 input, while bit seven corresponds to the IRQ15 input. A zero in a bit position sets up the respective IRQ input to recognize positive, edge-triggered interrupt requests (non-shareable). A one in a bit position sets the IRQ input up

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to recognize active low, level-sensitive interrupt requests (shareable). In both ELCR registers, bit 0 must be a zero.

DMA Controllers

The ISP contains two enhanced Intel 8237 DMA Controllers in a master slave configuration. Together, they provide a total of seven DMA channels. DMA channels five through seven may be used by 16-bit I/O devices, while channels zero through three are reserved for 8-bit I/O devices. Each of the DMA channels can be programmed to utilize the following EISA-specific features:

•8, 16 or 32-bit transfers.

•ISA compatible, Type “A,” Type “B” or Type “C” bus cycles..

•buffer chaining.

•ring buffer.

Detailed information on programming the DMA controllers can be found in the Intel 82350DT EISA Chipset manual.

When a DMA channel becomes bus master, the ISP depends on the EBC to run the bus cycle for the DMA channel. The EBC generates START#, CMD#, IORC# and IOWC#. When a DMA channel becomes bus master, the type of bus cycle to run is indicated by the ISP's ST[3:0] outputs. Table 12-11 defines the ST[3:0] output settings for the different types of DMA bus cycle types.

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