- •About This Book
- •Chapter 1: EISA Overview
- •Introduction
- •Compatibility With ISA
- •Memory Capacity
- •Synchronous Data Transfer Protocol
- •Enhanced DMA Functions
- •Bus Master Capabilities
- •Data Bus Steering
- •Bus Arbitration
- •Edge and Level-Sensitive Interrupt Requests
- •Automatic System Configuration
- •EISA Feature/Benefit Summary
- •Chapter 2: EISA Bus Structure Overview
- •Chapter 3: EISA Bus Arbitration
- •EISA Bus Arbitration Scheme
- •Preemption
- •Example Arbitration Between Two Bus Masters
- •Memory Refresh
- •Chapter 4: Interrupt Handling
- •ISA Interrupt Handling Review
- •ISA Interrupt Handling Shortcomings
- •Phantom Interrupts
- •Limited Number of IRQ Lines
- •EISA Interrupt Handling
- •Shareable IRQ Lines
- •Phantom Interrupt Elimination
- •Chapter 5: Detailed Description of EISA Bus
- •Introduction
- •Address Bus Extension
- •Data Bus Extension
- •Bus Arbitration Signal Group
- •Burst Handshake Signal Group
- •Bus Cycle Definition Signal Group
- •Bus Cycle Timing Signal Group
- •Lock Signal
- •Slave Size Signal Group
- •AEN Signal
- •EISA Connector Pinouts
- •Chapter 6: ISA Bus Cycles
- •Introduction
- •8-bit ISA Slave Device
- •16-bit ISA Slave Device
- •Transfers With 8-bit Devices
- •Transfers With 16-bit Devices
- •Standard 16-bit Memory ISA bus Cycle
- •Standard 16-bit I/O ISA bus Cycle
- •ISA DMA Bus Cycles
- •ISA DMA Introduction
- •8237 DMAC Bus Cycle
- •Chapter 7: EISA CPU and Bus Master Bus Cycles
- •Intro to EISA CPU and Bus Master Bus Cycles
- •Standard EISA Bus Cycle
- •General
- •Analysis of EISA Standard Bus Cycle
- •Performance Using EISA Standard Bus Cycle
- •Compressed Bus Cycle
- •General
- •Performance Using Compressed Bus Cycle
- •General
- •Analysis of EISA Burst Transfer
- •Performance Using Burst Transfers
- •DRAM Memory Burst Transfers
- •Downshift Burst Bus Master
- •Chapter 8: EISA DMA
- •DMA Bus Cycle Types
- •Introduction
- •Compatible DMA Bus Cycle
- •Description
- •Performance and Compatibility
- •Type A DMA Bus Cycle
- •Description
- •Performance and Compatibility
- •Type B DMA Bus Cycle
- •Description
- •Performance and Compatibility
- •Type C DMA Bus Cycle
- •Description
- •Performance and Compatibility
- •EISA DMA Transfer Rate Summary
- •Other DMA Enhancements
- •Addressing Capability
- •Preemption
- •Buffer Chaining
- •Ring Buffers
- •Transfer Size
- •Chapter 9: EISA System Configuration
- •ISA I/O Address Space Problem
- •EISA Slot-Specific I/O Address Space
- •EISA Product Identifier
- •EISA Configuration Registers
- •EISA Configuration Process
- •General
- •Configuration File Naming
- •Configuration Procedure
- •Configuration File Macro Language
- •Example Configuration File
- •Example File Explanation
- •Chapter 10: EISA System Buses
- •Introduction
- •Host Bus
- •EISA/ISA Bus
- •Chapter 11: Bridge, Translator, Pathfinder, Toolbox
- •Bus Cycle Initiation
- •Bridge
- •Translator
- •Address Translation
- •Command Line Translation
- •Pathfinder
- •Toolbox
- •Chapter 12: Intel 82350DT EISA Chipset
- •Introduction
- •EISA Bus Controller (EBC) and EISA Bus Buffers (EBBs)
- •General
- •CPU Selection
- •Data Buffer Control and EISA Bus Buffer (EBB)
- •General
- •Transfer Between 32-bit EISA Bus Master and 8-bit ISA Slave
- •Transfer Between 16-bit EISA Bus Master and 8-bit ISA Slave
- •Transfer Between 16-bit ISA Bus Master and 8-bit ISA Slave
- •Transfer Between 16-bit ISA Bus Master and 16-bit ISA Slave
- •Transfer Between 32-bit Host CPU and 32-bit Host Slave
- •Transfer Between 32-bit Host CPU and 8-bit ISA Slave
- •Transfer Between 32-bit Host CPU and 16-bit ISA Slave
- •Transfer Between 32-bit Host CPU and 16-bit EISA Slave
- •Transfer Between 32-bit Host CPU and 32-bit EISA Slave
- •Address Buffer Control and EBB
- •Host CPU Bus Master
- •EISA Bus Master
- •ISA Bus Master
- •Refresh Bus Master
- •DMA Bus Master
- •Host Bus Interface Unit
- •ISA Bus Interface Unit
- •EISA Bus Interface Unit
- •Cache Support
- •Slot-Specific I/O Support
- •Clock Generator Unit
- •I/O Recovery
- •Testing
- •ISP interface unit
- •82357 Integrated System Peripheral (ISP)
- •Introduction
- •NMI Logic
- •Interrupt Controllers
- •DMA Controllers
- •System Timers
- •Central Arbitration Control
- •Refresh Logic
- •Miscellaneous Interface Signals
- •Glossary
- •Index
Chapter 1: EISA Overview
up. System resources such as serial ports, parallel ports, VGA and other manu- facturer-specific functions can be fully configured programmatically.
The EISA expansion card manufacturer includes a configuration file with each expansion card shipped. The configuration files can be included with either new, fully-programmable EISA boards or switch-configured ISA or EISA products. The configuration files are used at system configuration time to automatically assign global system resources (such as DMA channels and interrupt levels), thus preventing resource conflicts between the installed expansion cards. For switch-configurable boards, the configuration files can be used to determine the proper assignment of resources and to instruct the user about the proper selection of switch settings.
To accomplish the automatic configuration of the system board and expansion cards, EISA uses slot-specific I/O port ranges. An EISA card using these ranges can be installed into any slot in the system without the risk of I/O range conflicts. These I/O ranges can be used for expansion card initialization or for normal I/O port assignments that are guaranteed not to conflict with any other expansion board installed in the system.
EISA also includes a product identification mechanism for system boards and EISA expansion cards. The product identifier allows products to be identified during the configuration and initialization sequences for the system and EISA expansion boards. EISA includes guidelines for selection of a product identifier. The identifier for each product is selected by the product manufacturer and does not need the approval of any other party in the industry. However, a manufacturer-specific ID is assigned to each vendor by BCPR Services, the firm that manages the EISA specification.
EISA Feature/Benefit Summary
Table 1-1 provides a summary of the key features and benefits of the Extended Industry Standard Architecture.
13
EISA System Architecture
Table 1-1. EISA Feature/Benefit Summary
|
Feature |
|
|
Benefit |
|
|
|
|
|
|
|
|
Backward compatible with all ISA |
|
|
Customer base retains value of installed ISA |
|
|
expansion boards |
|
|
cards. |
|
|
|
|
|
|
|
|
Board size |
|
|
63 square inches of board space permits imple- |
|
|
|
|
|
mentation of powerful, highly-integrated ex- |
|
|
|
|
|
pansion cards. |
|
|
|
|
|
|
|
|
+5Vdc at approximately 4.5A |
|
|
Ample power for expansion cards employing a |
|
|
available at each expansion slot |
|
|
large amount of highly-integrated logic. |
|
|
|
|
|
|
|
|
32-bit address and data buses |
|
|
Support for 4GB of memory and 32-bit transfers. |
|
|
|
|
|
|
|
|
Programmable levelor edge- |
|
|
Interrupt request lines may be shared by multi- |
|
|
triggered interrupt recognition |
|
|
ple devices. |
|
|
|
|
|
|
|
|
Enhanced DMA capabilities |
|
|
Both ISA and EISA DMA devices have access to |
|
|
|
|
|
memory above 16MB. New bus cycle types and |
|
|
|
|
|
32-bit data bus allow faster transfer speeds |
|
|
|
|
|
(rates of up to 33 MB/second). |
|
|
|
|
|
|
|
|
Bus Master Support |
|
|
Support for up to fifteen bus master expansion |
|
|
|
|
|
cards, fast burst bus transfers, automatic data |
|
|
|
|
|
bus steering and control line translation. |
|
|
|
|
|
|
|
|
Automatic system configuration |
|
|
Supports automatic configuration of the EISA |
|
|
|
|
|
system board and EISA expansion cards each |
|
|
|
|
|
time the system is powered up. Also provides |
|
|
|
|
|
help to the end user in configuring older ISA |
|
|
|
|
|
expansion cards. |
|
14