EISA System Architecture

to determine when the EISA slave is ready to end the transfer. The EBC turns off SDOE0#, SDOE1# and SDOE2# to cause the four data EBB data latches to stop outputting the four data bytes.

All four bytes have now been transferred to the 32-bit EISA slave. The EBC now activates HRDYO#, host ready output, to tell the host CPU that it's ok to end the bus cycle.

Address Buffer Control and EBB

Under the control of the EBC, the address EBB ensures that the address generated by the current bus master is seen by every host, EISA and ISA slave in the system. Along with the address the state of the M/IO# bus cycle definition line must be propagated onto the EISA and host address buses so EISA and host slaves can discern memory addresses from I/O addresses. Table 12-4 defines the EBC output signals used to control the address EBB. Figure 12-5 provides a functional view of the address EBB and illustrates the linkage between the EBC and the address EBB. The figure also illustrates the direction of address flow through the three latching transceivers when the host CPU, an ISA master or an EISA master is the bus master. Table 12-5 shows the state of each of the EBC's address EBB control lines when each type of master is running a bus cycle. Entries designated as “transparent” indicate that the latch control line is left active for the entire bus cycle, causing the respective latching transceiver to be transparent.

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EISA System Architecture

Host CPU Bus Master

Refer to tables 12-5 and 12-4 and figure 12-5 while reading this description. When the host CPU is bus master, the address on the host address bus, HA[31:2], and the state of the HM/IO# bus cycle definition line must be propagated onto the EISA address bus, consisting of LA[23:2], LA#[31:24] and M/IO#, and the lower part of the ISA address bus, SA[19:2].

The pulse on LALE# causes the address EBB to latch the address from the host bus. The active on HALAOE# and the steady active on HALE# gates latched host address onto the EISA address bus, LA[23:2] and LA#[31:24]. It should be noted that the upper Host/EISA Latching Transceiver inverts address bits 31:24. The pulse on SALE# latches LA[19:2] into the EISA/ISA Latching Transceiver, while the active on LASAOE# allows it to output the latched address onto the SA bus, SA[19:2].

EISA Bus Master

Refer to tables 12-5 and 12-4 and figure 12-5 while reading this description. When an EISA master is the bus master, the address on the EISA address bus, LA[23:2] and LA#[31:24], and the state of the M/IO# bus cycle definition line must be propagated onto the host address bus, consisting of HA[31:2] and HM/IO#, and onto the lower part of the ISA address bus, SA[19:2].

The active on LAHAOE# and the steady active on HALE# allows the address on the EISA address bus to flow onto the host address bus. The pulse on SALE# causes the lower part of the EISA address, LA[19:2], to be latched into the EISA/ISA latching transceiver, while the active on LASAOE# allows the latched LA address to be driven onto the SA bus, SA[19:2].

ISA Bus Master

Refer to tables 12-5 and 12-4 and figure 12-5 while reading this description. When an ISA master is the bus master, the address on the ISA address bus, SA[19:2] and LA[23:17], must be propagated onto the host address bus, HA[31:2], and onto the lower part of the EISA address bus, LA[23:2]. Since ISA bus masters do not use LA#[31:24], pull-up resistors force these lines inactive when an ISA bus master is placing an address on the address bus.

The steady active state of SALE# and the active state of SALAOE# allows the portion of the ISA address on SA[16:2] to flow through the EISA/ISA latching transceiver onto the lower part of the EISA address bus, LA[16:2]. The ISA bus

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master places address bits 23:17 directly onto LA[23:17] of the EISA/ISA address bus. The active on LAHAOE# and the steady active state of HALE# permits the address on the EISA address bus, LA[23:2] and LA#[31:24], to flow through onto the host address bus, HA[31:2]. The ones on LA#[31:24] are inverted by the upper Host/EISA latching transceiver before being driven onto HA[31:2]4.

Refresh Bus Master

Refer to tables 12-5 and 12-4 and figure 12-5 while reading this description. The Refresh logic is located in the ISP chip. When the Refresh logic becomes bus master and drives the next sequential row address onto the host address bus, the row address must be propagated onto the EISA and ISA addresses buses as well.

The active state of HALAOE# and the steady active state of LALE# allows the row address to flow from the host address bus, HA[31:2], to the EISA address bus, LA[31:2]. The pulse on SALE# latches the row address into the EISA/ISA latching transceiver and the active state of LASAOE# causes the row address to be driven onto the SA bus, SA[19:2]. The Refresh logic in the ISP also sets the HM/IO# bus cycle definition line high to indicate that a memory row address is on the bus. The EBC passes the state of the host bus HM/IO# line to the EISA M/IO# line.

DMA Bus Master

Refer to tables 12-5 and 12-4 and figure 12-5 while reading this description. The DMA controllers are located in the ISP chip and output a memory address onto the host address bus, HA[31:2], when a DMA channel becomes bus master. The HM/IO# line is also set high by the ISP to indicate that a memory address is present on the bus. The EBC must command the address EBB to pass the memory address and the state of HM/IO# onto the EISA address bus, LA[23:2] and LA#[31:24] plus M/IO#, and onto the ISA address bus, consisting of SA[19:2] and LA[23:17].

The active state of HALAOE# and the steady active state of LALE# allows the memory address on the host address bus, HA[31:2], to flow through the upper and lower Host/EISA latching transceivers onto the EISA data bus, LA[23:2] and LA#[31:24]. The pulse on SALE# latches the memory address on the host address bus, HA[31:2], into the EISA/ISA latching transceiver and the active state of LASAOE# allows the transceiver to drive it onto the SA bus, SA[19:2].

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