
- •About This Book
- •Chapter 1: EISA Overview
- •Introduction
- •Compatibility With ISA
- •Memory Capacity
- •Synchronous Data Transfer Protocol
- •Enhanced DMA Functions
- •Bus Master Capabilities
- •Data Bus Steering
- •Bus Arbitration
- •Edge and Level-Sensitive Interrupt Requests
- •Automatic System Configuration
- •EISA Feature/Benefit Summary
- •Chapter 2: EISA Bus Structure Overview
- •Chapter 3: EISA Bus Arbitration
- •EISA Bus Arbitration Scheme
- •Preemption
- •Example Arbitration Between Two Bus Masters
- •Memory Refresh
- •Chapter 4: Interrupt Handling
- •ISA Interrupt Handling Review
- •ISA Interrupt Handling Shortcomings
- •Phantom Interrupts
- •Limited Number of IRQ Lines
- •EISA Interrupt Handling
- •Shareable IRQ Lines
- •Phantom Interrupt Elimination
- •Chapter 5: Detailed Description of EISA Bus
- •Introduction
- •Address Bus Extension
- •Data Bus Extension
- •Bus Arbitration Signal Group
- •Burst Handshake Signal Group
- •Bus Cycle Definition Signal Group
- •Bus Cycle Timing Signal Group
- •Lock Signal
- •Slave Size Signal Group
- •AEN Signal
- •EISA Connector Pinouts
- •Chapter 6: ISA Bus Cycles
- •Introduction
- •8-bit ISA Slave Device
- •16-bit ISA Slave Device
- •Transfers With 8-bit Devices
- •Transfers With 16-bit Devices
- •Standard 16-bit Memory ISA bus Cycle
- •Standard 16-bit I/O ISA bus Cycle
- •ISA DMA Bus Cycles
- •ISA DMA Introduction
- •8237 DMAC Bus Cycle
- •Chapter 7: EISA CPU and Bus Master Bus Cycles
- •Intro to EISA CPU and Bus Master Bus Cycles
- •Standard EISA Bus Cycle
- •General
- •Analysis of EISA Standard Bus Cycle
- •Performance Using EISA Standard Bus Cycle
- •Compressed Bus Cycle
- •General
- •Performance Using Compressed Bus Cycle
- •General
- •Analysis of EISA Burst Transfer
- •Performance Using Burst Transfers
- •DRAM Memory Burst Transfers
- •Downshift Burst Bus Master
- •Chapter 8: EISA DMA
- •DMA Bus Cycle Types
- •Introduction
- •Compatible DMA Bus Cycle
- •Description
- •Performance and Compatibility
- •Type A DMA Bus Cycle
- •Description
- •Performance and Compatibility
- •Type B DMA Bus Cycle
- •Description
- •Performance and Compatibility
- •Type C DMA Bus Cycle
- •Description
- •Performance and Compatibility
- •EISA DMA Transfer Rate Summary
- •Other DMA Enhancements
- •Addressing Capability
- •Preemption
- •Buffer Chaining
- •Ring Buffers
- •Transfer Size
- •Chapter 9: EISA System Configuration
- •ISA I/O Address Space Problem
- •EISA Slot-Specific I/O Address Space
- •EISA Product Identifier
- •EISA Configuration Registers
- •EISA Configuration Process
- •General
- •Configuration File Naming
- •Configuration Procedure
- •Configuration File Macro Language
- •Example Configuration File
- •Example File Explanation
- •Chapter 10: EISA System Buses
- •Introduction
- •Host Bus
- •EISA/ISA Bus
- •Chapter 11: Bridge, Translator, Pathfinder, Toolbox
- •Bus Cycle Initiation
- •Bridge
- •Translator
- •Address Translation
- •Command Line Translation
- •Pathfinder
- •Toolbox
- •Chapter 12: Intel 82350DT EISA Chipset
- •Introduction
- •EISA Bus Controller (EBC) and EISA Bus Buffers (EBBs)
- •General
- •CPU Selection
- •Data Buffer Control and EISA Bus Buffer (EBB)
- •General
- •Transfer Between 32-bit EISA Bus Master and 8-bit ISA Slave
- •Transfer Between 16-bit EISA Bus Master and 8-bit ISA Slave
- •Transfer Between 16-bit ISA Bus Master and 8-bit ISA Slave
- •Transfer Between 16-bit ISA Bus Master and 16-bit ISA Slave
- •Transfer Between 32-bit Host CPU and 32-bit Host Slave
- •Transfer Between 32-bit Host CPU and 8-bit ISA Slave
- •Transfer Between 32-bit Host CPU and 16-bit ISA Slave
- •Transfer Between 32-bit Host CPU and 16-bit EISA Slave
- •Transfer Between 32-bit Host CPU and 32-bit EISA Slave
- •Address Buffer Control and EBB
- •Host CPU Bus Master
- •EISA Bus Master
- •ISA Bus Master
- •Refresh Bus Master
- •DMA Bus Master
- •Host Bus Interface Unit
- •ISA Bus Interface Unit
- •EISA Bus Interface Unit
- •Cache Support
- •Slot-Specific I/O Support
- •Clock Generator Unit
- •I/O Recovery
- •Testing
- •ISP interface unit
- •82357 Integrated System Peripheral (ISP)
- •Introduction
- •NMI Logic
- •Interrupt Controllers
- •DMA Controllers
- •System Timers
- •Central Arbitration Control
- •Refresh Logic
- •Miscellaneous Interface Signals
- •Glossary
- •Index

EISA System Architecture
A15
A14
A13
A12
A9
A8
AEN(from DMAC)
M/IO#
EISA
System
Board
I/O
Decoder
AEN0
AEN1
AEN2
AEN3
AEN4
AEN5
AEN6
AEN7
AEN8
AEN9 AEN10 AEN11
AEN12
AEN13
AEN14
AEN15
Figure 9-2. The System Board's AEN Decoder
EISA Product Identifier
EISA expansion boards, embedded devices and system boards have a four byte product ID that can be read from I/O port addresses xC80h – xC83h, where x = 0 for the system board or the number of the expansion slot the card is installed in. For example, the system board's ID can be read from I/O addresses 0C80 – 0C83h and slot one’s ID can be read from 1C80 – 1C83h.
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Chapter 9: EISA System Configuration
The first two bytes of the system board ID, read from I/O ports xC80 – xC81, contain a three character manufacturer's code. The three character manufacturer code is uppercase, ASCII alpha chosen by the manufacturer and registered with the firm that distributes the EISA spec. A compressed version of the ASCII code, using just the lower five bits of each character, is used. The third byte and the high-order four bits of the fourth byte are used to specify a product identifier consisting of three hex digits. The lower four bits of the fourth byte is use to specify the product revision number. Table 9-6 illustrates the format of the product ID bytes read from an expansion board. Table 9-7 illustrates the format of the product ID bytes read from an EISA system board.
To verify that an EISA expansion card is installed in a particular card slot:
•Write FFh to I/O port xC80h.
•Read one byte from xC80h.
•If the byte read equals FFh, an EISA card isn't installed in the slot. If the byte does not equal FFh and bit 7 of the byte read is zero, the card's EISA product ID can be read from xC80h – xC83h.
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Table 9-6. Expansion Board Product ID Format |
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Location/Bits |
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Specify |
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xC80, bit 7 |
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not used, must be 0 |
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xC80, bits 6:2 |
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1st compressed ASCII character of Manufacturer's ID |
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xC80, bits 1:0 |
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upper two bits of 2nd compressed ASCII character of Manufac- |
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turer's ID |
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xC81, bits 7:5 |
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lower three bits of 2nd compressed ASCII character of Manufac- |
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turer's ID |
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xC81, bits 4:0 |
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3rd compressed ASCII character of Manufacturer's ID |
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xC82, bits 7:4 |
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upper hex digit of product type |
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xC82, bits 3:0 |
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middle hex digit of product type |
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xC83, bits 7:4 |
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lower hex digit of product type |
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xC83, bits 3:0 |
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single hex digit of product revision number |
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EISA System Architecture
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Table 9-7. EISA System Board Product ID Format |
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Location/Bits |
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Specify |
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0C80, bit 7 |
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not used, must be 0 |
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0C80, bits 6:2 |
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1st compressed ASCII character of Manufacturer's ID |
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0C80, bits 1:0 |
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upper two bits of 2nd compressed ASCII character of Manufac- |
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turer's ID |
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0C81, bits 7:5 |
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lower three bits of 2nd compressed ASCII character of Manufac- |
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turer's ID |
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0C81, bits 4:0 |
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3rd compressed ASCII character of Manufacturer's ID |
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0C82, bits 7:0 |
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reserved for manufacturer's use |
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0C83, bits 7:3 |
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reserved for manufacturer's use |
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0C83, bits 2:0 |
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EISA bus version |
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EISA Configuration Registers
In an ISA machine, expansion cards are configured by setting DIP switches and/or jumpers to the desired settings. This allows the user to select options such as:
•the start address of a device ROM mounted on the card
•the start address of RAM located on the card
•the IRQ line the card utilizes
•the DMA channel the card utilizes
•the I/O address range the card responds to
Setting the switches and/or jumpers allows the user to resolve conflicts between installed expansion cards. In addition, many ISA system boards have switches and/or jumpers that are used to configure the system board options.
The EISA specification replaces the switches and/or jumpers with special I/O locations. Each of these I/O locations can contain up to eight bits that may be used to select options on the system or expansion card. Each I/O location may be thought of as a pseudo-DIP switch bank. They are configuration registers. These special I/O locations reside in the slot-specific I/O address space starting at xC80h and extending up to xCFFh, a total of 128 locations. The first four of these I/O locations are reserved for the card ID, while three of the eight bits in xC84h are reserved for special card functions. The remaining five bits in xC84h and locations xC85h – xCFFh are available for the implementation of cardspecific configuration registers.
Configuration Bits Defined by EISA Spec
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