EISA System Architecture

Table 8-7. Type C Transfer Rates

When a DMA channel is programmed to use the Type C DMA bus cycle to transfer data, the channel may only be used to transfer data between fast, EISA memory and an I/O device designed for Type C transfers. No ISA I/O devices will work with a channel programmed for Type C bus cycles.

EISA DMA Transfer Rate Summary

Table 8-8 indicates the maximum data transfer rates achievable for each DMA bus cycle type, and the expansion devices that are compatible with the bus cycle type.

Table 8-8. EISA DMA Transfer Rates

Other DMA Enhancements

Addressing Capability

The EISA DMA controller generates full 32-bit addresses, giving it the ability to transfer data to or from memory throughout the full 4GB address range.

88

Chapter 8: EISA DMA

Preemption

When a DMA channel is programmed for Type A, Type B, or Type C bus cycles, it may be preempted by the CAC if another device requires the use of the bus. When a channel is programmed for ISA-compatible DMA bus cycles, however, it cannot be preempted. This means that it can prevent other devices from receiving the use of the bus on a timely basis if the channel is programmed for a lengthy block or demand mode transfer. Care should therefore be exercised.

When the CAC detects another device that requires the use of the bus, it removes the bus grant from the DMA controller. The active DMA channel releases the bus within four microseconds.

Buffer Chaining

The EISA DMA controller's buffer chaining function permits the implementation of scatter write and gather read operations. A scatter write operation is one in which a contiguous block of data is read from an I/O device and is written to two or more areas of memory, or buffers. A gather read operation reads a stream of data from several blocks of memory, or buffers, and writes it to an I/O device.

The programmer writes the start address of the first memory buffer to the DMA channel and sets the channel's transfer count equal to the number of bytes, words, or doublewords to be transferred to or from the first buffer. The programmer then enables chaining mode, causing the DMA channel to load the start memory address and transfer count into another set of channel registers, known as the current registers. The programmer then writes the start address of the second memory buffer to the DMA channel and sets the channel's transfer count equal to the number of bytes, words, or doublewords to be transferred to or from the second buffer.

When the DMA channel has exhausted the first transfer count, the channel automatically loads the current registers from the secondary registers and generates either TC or an IRQ13. If the channel was programmed by the main CPU, IRQ13 is generated. If the channel was programmed by an EISA bus master, TC is generated instead. The TC or IRQ13 informs the bus master or microprocessor that the first buffer transfer has been completed, the second buffer transfer is in progress and the start address and transfer count for the third

89

EISA System Architecture

buffer transfer (if there is one) should be written to the channel's registers. Updating these registers causes the controller to de-activate TC or IRQ13.

The channel generates a Transfer Complete (TC) when the transfer count is exhausted and the channel's registers have not been reloaded.

Ring Buffers

The EISA DMA controller allows the programmer to implement a ring buffer. If enabled, the ring buffer reserves a fixed range of memory to be used for a channel. The start and end address of the ring buffer are defined by the start memory address and the transfer count. As data is read from the I/O device it is written into the ring buffer in memory. When the DMA transfer has exhausted its transfer count, the channel automatically reloads the start memory address and transfer count registers and continues with the DMA transfer from the I/O device. The new data is written into memory at the start of the ring buffer, over-writing the older information that has already been read by the microprocessor. As the programmer reads information that was deposited in the ring buffer by the channel, the programmer must update the channel's stop register with the memory address of the next location that has not yet been read by the microprocessor. The stop register prevents the DMA channel from over-writing information that the microprocessor hasn't read yet.

Transfer Size

Each DMA channel can be programmed to perform either 8, 16 or 32-bit transfers.

90