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Chapter 8: EISA DMA |
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Table 8-2. ISA-Compatible Transfer Rates |
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I/O Device Size |
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Transfer Rate |
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8-bit |
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1.0416MB/second |
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16-bit |
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2.0833MB/second |
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32-bit |
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4.1666MB/second |
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When programmed to use the ISA-compatible DMA bus cycle, a DMA channel may be used to transfer data between an ISA-compatible I/O device and memory.
Type A DMA Bus Cycle
Description
When programmed to use Type A DMA bus cycles, a transfer is performed every six BCLK periods. Table 8-3 defines the duration of key signals during a Type A DMA bus cycle.
Table 8-3. The DMA Type A Bus Cycle
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Event |
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Duration |
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Memory address present |
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6.0 BCLKs |
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Duration of data transfer period during a memory to IO transfer |
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3.5 BCLKs |
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(CMD# active) |
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Duration of IORC# during I/O to memory transfer |
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4.5 BCLKs |
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Duration of IOWC# during a memory to IO transfer |
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3.0 BCLKs |
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The duration of the key signals illustrated in table 8-3 defines the amount of time the memory and I/O device have to recognize that they are being addressed and to either accept or output data. When performing Type A bus cycles, the DMA controller uses W/R# rather than MRDC# or MWTC# to indicate the type of memory operation,.
Performance and Compatibility
Table 8-4 defines the data transfer rates when a DMA channel is programmed to use the Type A DMA bus cycle to transfer data.
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