Chapter 8: EISA DMA

Chapter 8

The Previous Chapter

The previous chapter described the bus cycle types that may be run by the main CPU or an EISA bus master.

This Chapter

This chapter describes the EISA DMA capability. This includes a description of the EISA DMA bus cycle types and other capabilities of the EISA DMA controller.

The Next Chapter

The next chapter provides an introduction to the bus structure hierarchy in a typical EISA system. It describes the distribution of functions between the host bus, EISA bus and the X-bus on the typical EISA system board and the relationship of the functional areas to each other.

DMA Bus Cycle Types

Introduction

The EISA DMA controller incorporates seven DMA channels, each capable of performing 8, 16 or 32-bit transfers. In addition, each DMA channel may be individually programmed to utilize one of four types of bus cycles when performing data transfers between an I/O device and memory. The following sections describe the bus cycle types and other DMA improvements. Detailed timing diagrams and register-level programming information may be found in the EISA specification.

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