EISA System Architecture

Performance Using Burst Transfers

Once a 32-bit bus master and a 32-bit slave have switched into burst mode, the second through the last transfers may be completed at the following rate:

8.33MHz BCLK = 120ns per BCLK cycle

1 second/120ns per transfer = 8.33M transfers/second

8.33M transfers/second x 4 bytes per transfer = 33.33MB/second

If the bus master and/or the slave are 16-bit devices, the maximum transfer rate would be 16.66MB/second.

DRAM Memory Burst Transfers

The addresses output by the bus master when bursting to or from Page Mode or Static Column (SCRAM) memory must be within a 1024 byte DRAM memory row (address lines LA[31:10] cannot change during the burst). The addresses within the burst do not have to be sequential. They only have to be within the same row. To change DRAM rows, the burst transfer must be terminated by the bus master by setting MSBURST# deasserted on the last cycle in the row, and the burst sequence is then restarted within a new row.

Downshift Burst Bus Master

A downshift burst bus master is a 32-bit burst bus master that can convert to a 16-bit burst bus master on-the-fly. In other words, if the bus master samples EX16# and SLBURST# asserted at the end of Ts, it automatically adjusts itself to only use the lower two data paths during the burst. The bus master is responsible for copying data to the appropriate data paths during the burst. The system board data bus steering logic will not take care of data copying. At the start of the first transfer in the burst, the downshift bus master must indicate its ability to downshift by setting MASTER16# asserted while START# is asserted (in other words, for the duration of the address phase).

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