Chapter 6: ISA Bus Cycles

Standard 16-bit I/O ISA bus Cycle

Figure 6-3 illustrates the timing of a bus cycle on the ISA bus when the current bus master is communicating with a 16-bit I/O device. Each of the numbered steps corresponds to the numbered reference points in figure 6-3.

1.If the system board is based on an 80286 or 80386 microprocessor and address pipelining is active, the address is present on the LA bus prior to the beginning of the bus cycle. The LA bus has no impact on I/O bus cycles since A[23:16] always contain zeros during I/O operations.

2.BALE is asserted halfway through the address phase, gating the address through the system board's address latch onto the SA bus.

3.If this is a write bus cycle, the microprocessor's output data is gated onto the SD bus half-way through the address phase and remains on the SD bus until half a BCLK cycle into the next bus cycle (half-way through the address phase of the next bus cycle).

4.At the start of the first data clock period, the trailing-edge of BALE causes the address latch on the system board to latch the lower twenty bits of the address, SA[19:0], so that it remains static on the SA bus for the remainder of the bus cycle. Slave devices can safely latch the SA address on the bus on the falling edge of BALE (if they haven’t done so already).

5.The appropriate command line (IORC# or IOWC#) is also asserted at the midpoint of the first data clock period. This command line remains asserted until the end of the bus cycle (end of last Tc).

6.At the midpoint of the first data clock period, the default ready timer on the system board ignores the NOWS# line (since an I/O device is being accessed). This is done to prevent two back-to-back I/O write bus cycles from accessing the I/O device too quickly. This could violate the I/O write recovery time of the I/O device, causing improper operation.

7.During address pipelining, the microprocessor is free to output the address for the next bus cycle during the current bus cycle. Only the upper portion of the pipelined address appears at this time on the LA bus because these bits are buffered but not latched from the microprocessor's address bus. The remainder of the new address does not appear on the SA bus until the midpoint of the address phase of the next bus cycle.

8.IO16# is sampled at the midpoint of the second data clock period to determine if the I/O device is an 8 or 16-bit device. If sampled asserted, data bus steering is not performed and the bus cycle is terminated on the next risingedge of BCLK (the end of the second data clock period). The bus cycle is not terminated if the CHRDY line is sampled deasserted.

9.CHRDY is sampled by the default ready timer at the end of the second data clock period to determine if the device is ready to complete the bus cycle. If

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the device cannot complete the bus cycle by the end of the second BCLK cycle, it must deassert CHRDY. If CHRDY is sampled deasserted by the default ready timer, it responds by extending the bus cycle by one data clock period. CHRDY is then checked at the beginning of each additional data clock period until the device releases CHRDY to indicate that the bus cycle can be completed.

10.An ISA 16-bit I/O bus cycle defaults to three BCLK cycles (one wait state) if CHRDY stays asserted throughout the bus cycle. The bus cycle cannot be terminated earlier by the assertion of NOWS#. This means that the length of an ISA bus cycle when accessing a 16-bit I/O card defaults to one wait state unless lengthened by the deassertion of CHRDY. READY# is then asserted to the microprocessor, telling it to read the data from the data bus (if this is a read transaction). When an I/O write bus cycle terminates, the IOWC# command line is de-activated, but the data remains on the SD bus until the end of the first half of the address phase in the next bus cycle. This accommodates the hold time of the device being written to and doesn't disturb the device being addressed in the next bus cycle because the command line for that bus cycle hasn't been activated yet.

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Chapter 6: ISA Bus Cycles

BCLK

LA17:LA23

SBHE#,

SA0:SA19

BALE

5

IORC#, IOWC#

6

NOWS#

9

CHRDY

10

Read Data SD0:15

3

Write Data

SD0:15

Figure 6-3. Standard Access to 16-bit I/O Device

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EISA System Architecture

Zero Wait State ISA Bus Cycle

Accessing 16-bit Device

Figure 6-4 illustrates the timing of a bus cycle on the ISA bus when the current bus master is communicating with a zero wait state 16-bit device. Note that only 16-bit memory devices can complete bus cycles at zero wait states. Each of the numbered steps corresponds to the numbered reference points in figure 6-4.

1.In this example, address pipelining is active and the LA address is present on the ISA bus prior to the beginning of the bus cycle. This allows the addressed slave to start decoding the address early. In some cases, this allows a device to operate at zero wait states.

2.BALE is asserted halfway through the address phase. On the rising-edge of BALE, 16-bit ISA memory devices can begin to decode the LA lines to determine if the address is for them. When BALE is asserted, the lower portion of the address from the processor is transferred through the system board's address latch onto the SA bus.

3.The addressed memory board asserts M16# as a result of decoding the LA lines, indicating to the system board's bus control logic that it is capable of handling a 16-bit transfer without data bus steering being performed by the steering logic on the system board.

4.If this is a write bus cycle, the microprocessor's output data is gated onto the SD bus half-way through the address phase and remains on the SD bus until half a BCLK cycle into the next bus cycle (half-way through the address phase of the next bus cycle).

5.At the end of the address phase, the trailing-edge of BALE causes two events to take place:

a)16-bit ISA memory devices latch the LA lines so the addressed device will not be deselected if the LA lines are pipelined before the end of the current bus cycle.

b)the address latch on the system board latches the lower twenty bits of the address, SA[19:0], so that they remain static on the SA bus for the remainder of the bus cycle. Slave devices can safely decode the SA address on the bus on the falling edge of BALE (if they haven’t done so already).

6.The system board's bus control logic samples M16# at the end of the address phase to determine if the addressed device can take advantage of the MRDC# or MWTC# command line being asserted immediately. M16# is sampled asserted and the appropriate command line (MRDC# or MWTC#) is asserted at the leading edge of the first data clock period. This command line remains asserted until the end of the bus cycle (end of Tc).

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Chapter 6: ISA Bus Cycles

7.If M16# was not sampled asserted the firts time, the system board's bus control logic samples M16# a second time at the midpoint of the first data clock period to determine if data bus steering is necessary. Since this is an access to a 16-bit device, no steering is necessary. Since the M16# line is asserted, the default ready timer samples the NOWS# line to determine if the bus cycle can end in zero wait states. In this example, M16# is sampled asserted, forcing the default ready timer to assert the microprocessor's READY# line before the end of the current data clock period. In this way, faster ISA memory boards can complete a bus cycle in two rather than three BCLK cycles.

8.Since the LA lines have already done their job, (the addressed device has already decoded the LA lines and latched the chip select), the microprocessor is free to output the address for the next bus cycle.

9.During a read, the microprocessor latches the contents of the data bus, thereby ending the bus cycle. During a write, the microprocessor ends the bus cycle.

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EISA System Architecture

BCLK

LA17:LA23

SBHE#,

SA0:SA19

2 5

BALE

MRDC#

MWTC#

6

M16#

3 7

NOWS#

CHRDY

9

Read Data

SD0:15

4

Write Data

SD0:15

Figure 6-4. Zero Wait State Access to a 16-bit ISA Memory Device

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