4.6Integration test summary

Table 4-7 PrimeCell SCI integration test strategy

Name

Type

Source/

Test strategy

destination

PRESETn

Input

Reset controller

Not tested using integration test vectors

PADDR [11:2]

Input

APB

Register read/write

PCLK

Input

APB

Register read/write

PENABLE

Input

APB

Register read/write

PRDATA [15:0]

Output

APB

Register read/write

PSEL

Input

APB

Register read/write

PWDATA [15:0]

Input

APB

Register read/write

PWRITE

Input

APB

Register read/write

SCICLK

Input

Clock generator

Not tested using integration test vectors

nSCIRST

Input

Reset controller

Not tested using integration test vectors

SCITXTIDEINTR

Output

Interrupt controller

Using SCIITOP1 register

SCIRXTIDEINTR

Output

Interrupt controller

Using SCIITOP1 register

SCICLKACTINTR

Output

Interrupt controller

Using SCIITOP2 register

SCICLKSTPINTR

Output

Interrupt controller

Using SCIITOP2 register

SCIRORINTR

Output

Interrupt controller

Using SCIITOP2 register

SCIRTOUTINTR

Output

Interrupt controller

Using SCIITOP1 register

SCICHTOUTINTR

Output

Interrupt controller

Using SCIITOP1 register

SCIBLKTOUTINTR

Output

Interrupt controller

Using SCIITOP1 register

SCIATRDOUTINTR

Output

Interrupt controller

Using SCIITOP1 register

SCIATRSOUTINTR

Output

Interrupt controller

Using SCIITOP1 register

SCITXERRINTR

Output

Interrupt controller

Using SCIITOP1 register

SCICARDDNINTR

Output

Interrupt controller

Using SCIITOP1 register

ARM DDI 0228A

Copyright © 2001 ARM Limited. All rights reserved.

4-17

Name

Type

Source/

Test strategy

destination

SCICARDUPINTR

Output

Interrupt controller

Using SCIITOP1 register

SCICARDOUTINTR

Output

Interrupt controller

Using SCIITOP1 register

SCICARDININTR

Output

Interrupt controller

Using SCIITOP1 register

SCIINTR

Output

Interrupt controller

Using SCIITOP2 register

SCITXDMASREQ

Output

DMA controller

Using SCIITOP1 register

SCIRXDMASREQ

Output

DMA controller

Using SCIITOP1 register

SCITXDMABREQ

Output

DMA controller

Using SCIITOP1 register

SCIRXDMABREQ

Output

DMA controller

Using SCIITOP1 register

SCITXDMACLR

Input

DMA controller

Using SCIITIP register

SCIRXDMACLR

Input

DMA controller

Using SCIITIP register

SCICLKIN

Input

Pad

Using integration vector trickbox and SCIITIP and

SCIITOP2 registers

SCIDATAIN

Input

Pad

Using integration vector trickbox and SCIITIP and

SCIITOP2 registers

SCIDEACREQ

Input

Pad

Using integration vector trickbox and SCIITIP and

SCIITOP2 registers

SCIDETECT

Input

Pad

Using integration vector trickbox and SCIITIP and

SCIITOP2 registers

nSCICLKEN

Output

Pad

Using integration vector trickbox and SCIITIP and

SCIITOP2 registers

nSCICLKOUTEN

Output

Pad

Using integration vector trickbox and SCIITIP and

SCIITOP2 registers

SCICLKOUT

Output

Pad

Using integration vector trickbox and SCIITIP and

SCIITOP2 registers

nSCIDATAEN

Output

Pad

Using integration vector trickbox and SCIITIP and

SCIITOP2 registers

nSCIDATAOUTEN

Output

Pad

Using integration vector trickbox and SCIITIP and

SCIITOP2 registers

4-18

Copyright © 2001 ARM Limited. All rights reserved.

ARM DDI 0228A

Programmer’s Model for Test

Table 4-7 PrimeCell SCI integration test strategy (continued)

Name

Type

Source/

Test strategy

destination

SCIDEACACK

Output

Pad

Using integration vector trickbox and SCIITIP and

SCIITOP2 registers

SCIVCCEN

Output

Pad

Using integration vector trickbox and SCIITIP and

SCIITOP2 registers

nSCICARDRST

Output

Pad

Using integration vector trickbox and SCIITIP and

SCIITOP2 registers

SCIFCB

Output

Pad

Using integration vector trickbox and SCIITIP and

SCIITOP2 registers

SCANENABLE

Input

Test controller

Not tested using integration test vectors

SCANINPCLK

Input

Test controller

Not tested using integration test vectors

SCANINSCICLK

Input

Test controller

Not tested using integration test vectors

SCANOUTPCLK

Output

Test controller

Not tested using integration test vectors

SCANOUTSCICLK

Output

Test controller

Not tested using integration test vectors

ARM DDI 0228A

Copyright © 2001 ARM Limited. All rights reserved.

4-19

4-20

Copyright © 2001 ARM Limited. All rights reserved.

ARM DDI 0228A

ARM DDI 0228A

Copyright © 2001 ARM Limited. All rights reserved.

A-1