clrf LCDcount

clrf LCDline

;Read data from EEPROM memory, starting at address 0

;and display on LCD until 0x0d terminator

;At this point character read is not 0x0d

;Display on LCD

The Ser2EEP program can be tested with any PC serial communications program set for the program’s protocol parameters. We developed and tested the program using Windows Hyperterminal.

15.1 EEPROM Devices and Interfaces

In addition to onboard EEPROM memory that is available in many PICs, a circuit can contain EEPROM memory in separate integrated circuits. The reason for using separate EEPROM is the need for storing more data, since access to onboard EEPROM memory is usually faster, simpler, and requires less interface elements.

EEPROM devices are furnished in two different interface types: serial and parallel. Devices that use the parallel bus require an 8-bit data bus and an address bus wide enough to cover its entire memory space. Although parallel EEPROMS are faster than serial ones, in PIC and microcontroller technology, parallel devices are usually out of the question.

Serial EEPROMS also come in various flavors. In the PIC environment, the most used ones are I2C (Inter-Integrated Circuit), SPI (Serial Peripheral Interface), and

Microwire which is a subset of SPI. Another interface called 1-Wire, similar to I2C, finds some use in PIC systems.

Although of different design and having unique architectures, the several types of EEPROM devices share many features. For example, they all operate on a three-phase system that includes an Opcode, an Address, and a Data phase. Although each type of device has a unique instruction set, the basic operations perform similar functions: enable write, enable read, get read status, get write status, read data, and write data. For this reason we have selected a single one of these interfaces: I2C. This interface, probably because of its minimal use of communications lines, seems to be the most popular one in the PIC environment.

15.1.1 The I2C Serial Interface

I2C (or I2C) is a serial computer bus and interface developed by Philips Electronics for use in TV receivers. I2C has found considerable use in embedded systems and is supported by many types of devices; including EEPROMs, thermal sensors, real-time clocks, RF tuners, video decoders, etc. I2C devices are made by Philips, National

Semiconductors, Microchip, and many others. The popularity of I2C is often attributed to its simplicity, low implementation cost, and minimal use of communications resources.

The typical use of I2C is for interfacing devices on a single board or in a closed system. The interface uses a two-wire bus and two signals: SDA (serial data line) and SCL (serial clock line). These signals support serial transmission 8-bits at a time with 7-bit address-space devices. In the I2C protocol the device that initiates a transaction is called the master and the device being addressed is the slave. Normally the master controls the clock signal, but the slave can hold-off the master in the middle of a transaction by pulling the SCL line low. This is called “.” Not all I2C slave devices support this feature.

The presence of a clock signal makes I2C a synchronous protocol. Since the clock signal is part of the transmission, it can vary without disrupting data. For this reason, I2C is used in systems with imprecise clocks, such as the PIC RC oscillator.

Every I2C hardware slave device has a predefined device address, although some part of this address can be defined at the board level. At the start of every transaction, the master sends the device address of the slave it intends to access. The slave device monitors the bus and responds only to commands that include its own address. The number of available user-configurable address bits limits the number of identical devices that coexist on the same bus.

15.1.2 I2C Communications

SDA and SCL I2C signals are open-drain, that is, the master and slave devices can only drive the lines low, or leave them open (high). In operation, a termination resistor pulls the line up to Vcc if no I2C device is pulling it down. It is this mechanism that allows a slave device to suspend communications by holding down the SCL line. Furthermore, I2C lines can only be in one of two states, called “float high” and “drive low.” Here again, it is the pull-up resistors that ensure that the line does not float in an unknown state.

The pull-up resistors used in I2C hardware vary according to communication speed. Typically, lines at 100 kbps require 4.7K pull-up resistors and lines at 400 kbps 1K resistors.

15.1.3 EEPROM Communications Conditions

The descriptions and examples that follow are limited to EEPROM IC2 device acess. I2C is a bidirectional interface, implemented by an Acknowledge or Ack system. This system allows data to be sent in one direction to one device on the I2C bus. The device indicates that data has been received by issuing an Ack signal. This action from the receiver eliminates any doubts about whether the transmission was received or not.

Several so-called “conditions” serve to explain I2C communications. The conditions refer to the various bus states during transmission, such as start, stop, data, and acknowledge.

The START condition (represented by the letter S) indicates that an R2C device is ready to transfer data on the bus. The device initializes the transmission by pulling the SDA line low. Recall that both lines are high in the normal state. So the S condition is detected by a low SDA and a high SCL.

The STOP condition (represented by the letter P) indicates that a device has finished transferring and is releasing the bus. The P condition is detected when the SDA line is released while the SCL line remains high. Thus, by action of the pull-up resistor, the P conditions places both lines high.

The RESTART condition (represented by the letter R) indicates that a device is ready to transmit more data without releasing the line. This condition is called a Repeated Start (condition Rs) in the technical literature. The typical scenario for an R condition is when a START must be sent, but a STOP has not occurred. The

RESTART condition issues a new START without releasing the line, as is the case when another data item must be sent. In the R condition, the SCL line is momentarily released while the SDA is held high.

The DATA TRANSFER condition (or just DATA condition) represents the transmission of 8 data bits by pulsing the SDA line while the SCL is high. The CLK signal and the SDA signal must be aligned so that the high and low bits on the SCL line coincide with the high state of the CLK line. The fact that the SCL line is meaningful only when the CLK signal is high allows the SCL line to change. A DATA byte can be a control code, an address, or an information element.

The ACK condition (represented by the letter A) is used to acknowledge a data reception. This condition is furnished by the device by bringing the SDS line low during the 9th clock pulse of a transmission sequence. The sequence starts with the S or R condition (one bit), followed by 8 data bits, and the 9th bit on the line requires that the SDA line be brought low, since the SDA line floats high.

Note in Figure 15-6 that the first command from master to slave is a Control In byte to indicate that an address follows. Once the address is acknowledged, the master sends the restart command (R condition) and a Control Out command indicating that the master is requesting a read operation. The EEPROM then acknowledges and sends the data, to which the master responds with NACK to instruct the

EEPROM that no more data is required.

In both read and write sequences, each byte transmitted requires a response from the other element. This response can be either an ACK (condition A) or a NACK (condition N). The RESTART bit that preceded the Control Out command is necessary since the P condition (STOP bit) has not been sent. The I2C protocol requires that the START condition be sent only on an idle bus, and never in the middle of a transmission.

Read and write operations to large EEPROMS, those with a two-byte address space, are identical to the ones described, except that there are two address bytes. The first one holds the high-order element and the second one the low-order. Here again, each byte transmitted must be acknowledged by the receiver.

15.1.6 I2C EEPROM Devices

EEPROM ICs that conform to the I2C specification are available to the PIC circuit designer. Microchip (the same company that manufactures the PIC microcontrollers) markets a series of I2C chips for this purpose. The line is designated as the 24XXX series of serial EEPROM devices. Table 15.1 lists several I2C EEPROM devices available from Microchip.

Table 15.1

I2C Compatible Serial EEPROM Devices from Microchip

The memory capacity of the various EEPROM ICs ranges from 16 bytes to 128K. Since up to four 128K devices can be cascaded, the total accessible memory goes up to 512K. In selecting a particular IC one must take into account several parameters, since the page size, the maximum clock speed, and the number of similar devices that can be grouped changes within the same device type. In the example developed later in this chapter, we used the 24LC04B EEPROM with a total of 512 bytes located in two memory banks.

Figure 15-9 SFRs Associated with I2C Operations

Several 16F87x registers relate to MSSP operation in I2C mode. Figure 15-9 shows these SFRs.

In the following subsection we discuss the registers and bits that apply to MSSP operation in Master Mode.

MSSP in Master Mode

In the context of accessing EEPROM circuits, the MSSP is operated in master mode. At this point we should consider that although the EEPROM device operates as a slave, it is a “smart” slave since it has a control engine capable of performing operations on its own, including reading and writing to its address space, recognizing commands, and issuing the corresponding responses. For example, in a data write operation the master sends the corresponding command code, followed by the address to which the data is to be written, followed by the data itself. The peripheral (in this case the EEPROM IC) receives and acknowledges the various bytes and executes the requested operations. In the case of a read command the EEPROM fetches and returns the data from the memory address requested in the command.

One of the special function registers most used in MSSP master mode operations is the SSPCON. Figure 15-10 is a bitmap of this register when operating in I2C master mode.