•A/D Conversion Complete Interrupt

•LCD Interrupt

•Data EEPROM Write Complete Interrupt

•Timer Overflow Interrupt

•CCP Interrupt

•SSP Interrupt

Several SFRs are related to the interrupt systems. The INTCON register provides interrupt enabling and control and the PIE1, PIE2, PIR1, and PIR2 registers have specific device-related functions. Programming interrupts is discussed in the context of the corresponding operations later in this book.

8.2 Mid-Range CPU and Instruction Set

In a digital system, the central processing unit (CPU) is the component that executes the program instructions and processes data. It provides the fundamental functionality of a digital system and is responsible for its programmability. In the PIC architecture, the CPU is the part of the device which fetches and executes the instructions contained in a program.

The arithmetic-logic unit (ALU) is the CPU element that performs arithmetic, bitwise, and logical operations. It also controls the bits in the STATUS register as they are changed by the execution of the various program instructions. For example, if the result of executing an instruction is zero, the ALU sets the zero bit in the STATUS register.

8.2.1 Mid-Range Instruction Set

The mid-range PIC instruction set consists of 35 instructions, divided into three general groups:

1.Byte-oriented and byte-wise file register operations

2.Bit-oriented and bit-wise file register operations

3.Literal and control instructions

Table 8.1 lists and briefly describes each instruction in the mid-range set.

Table 8.1

Mid-range PIC Instruction Set

(continues)

The STATUS register can be the destination for any instruction. If it is, and the Z, DC, or C bits are affected, then the write operation to these bits is disabled. In addition, the TO and PD bits are not writable.

Some instructions may have an unexpected action on the STATUS register bits, for example, the instruction

Clrf STATUS

clears the upper 3 bits, sets the Z bit, and leaves all other bits unchanged. For this reason, it is recommended that only instructions that do not change the Z, C, and DC bits be used to alter the STATUS register. The only ones that qualify are BCF, BSF, SWAPF, and MOVWF.

The OPTION register is actually named the OPTION_REG to avoid name clash with the option instruction. The OPTION_REG register contains several bits related to interrupts, the internal timers, and the watchdog timer. Figure 8-6 is a bitmap of the OPTION_REG register.

1= Increment on high-to-low transition on T0CKI pin

0 = Increment on low-to-high transition on T0CKI pin

bit 3 PSA: Prescaler Assignment bit

1 = Prescaler is assigned to the WDT

0 = Prescaler is assigned to the Timer0 bit 2-0 PS2:PS0:

Prescaler Rate Select bits

Figure 8-6 Bitmap of the OPTION_REG Register