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350

Chapter 14

equipment. The standard also finds use in large sound systems, such as those found in theaters and music events. EIA-485 does not specify any connector.

EIA-485 in PIC-based Systems

In PIC-based systems, EIA-485 is often used to provide strong serial signals that can travel up to 4000 ft at high baud rates in noisy electrical environments. Only two wires are needed to carry the EIA-485 signals. These are usually labeled the A and B lines. Once the A/B data line is established, up to 32 devices can be connected to it. The system is referred to as an EIA-485 network.

Implementing the EIA-485 network requires some way of converting the 485 signal levels to the TTL-levels in the PIC circuit. This is accomplished by means of a dedicated IC, such as the Texas Instruments Differential Bus Transceiver chip named the SN75176. The chip actually converts 485 signals to RS-232-C TTL-level signals. This allows devices that traditionally communicate over RS-232-C serial connections to communicate over a two-wire EIA-485 network. Figure 14-6 shows the pin diagram of the SN75176.

RO

_RE

DE

DI

18 Vcc

27 B

SN75176

36 A

45 GND

SN75176 PINOUT

B - Inverting receiver input Vcc - 4.75 to 5.25 V DC

RO - Receiver output

_RE - Receiver output enable

A - Non-inverting receiver input GND - Ground

DI - Driver input

DE - Driver output enable

Figure 14-6 Pin Out of the SN75176 IC

In addition to the SN75176, an EIA-485 circuit requires a 485 chip such as the MAX485. In PIC-based systems, the EIA-485 is sometimes used to communicate with multiple devices in a chain. It uses the same 8-bit asynchronous serial communications format as was described previously for RS-232-C.

14.2 Parallel Data Transmission

Parallel communications is the process of sending several bits of data simultaneously over individual data lines. In the computer environment, parallel communications are often associated with a popular printer interface developed by Centronics and sometimes called the Centronics or printer interface. Originally, the Centronics interface was designed for one-way communications. Later, it was made bi-directional, allowing its use in high-speed data transfers. The Centronics or parallel printer interface is now considered a legacy port.

Communications

351

In PIC-based systems, parallel communications often refer to the general principle rather than to the specific Centronics implementation. For example, wiring an 8-line toggle switch to the eight pins of the 16F85 Port-B line provides parallel communications between the switch and the PIC.

PIC circuits that use parallel data transfers offer many advantages. In the first place, parallel transmission is fast and the software is simple to develop. The hardware implementation is straightforward and does not require many additional components. Examples are connecting a multiple toggle switch to each of the lines of a PIC input port, or each of the pins of a seven-segment LED to the various pins of a PIC output port. The disadvantages of parallel systems are the distance limitations and the cost in system resources. Furthermore, parallel data transfers do not work well for data transmission over long distances. Many of the circuits and programs covered in previous chapters use parallel data transmission techniques. Since

PIC-based systems rarely communicate with parallel printers or use the Centronics standard for data transfer, no further discussion of the Centronics standard is justifiable in this context.

14.2.1 PIC Parallel Slave Port (PSP)

Some PICs are equipped with an 8-bit Parallel Slave Port module (PSP). At present, the PSP is multiplexed onto Port D and is found in PICs of the mid-range family, such as the 16F877. The PSP is also called the microprocessor port.

The PSP module provides an interface mechanism with one or more microprocessors. The parallel slave port has an operating speed of 200 ns with a clock rate of 20 MHz, as well as several on-chip peripheral functions for implementing real world interfaces.

In PICs equipped with the PSP, the parallel slave port functions are assigned to Port D, with some Port E bits providing control signals. To initialize PSP mode, data direction bits in the TRISE register that correspond to RD, WR, and CS (TRISE<2:0>) are configured as inputs and the control bit PSPMODE (TRISE) is set. When the PSP mode is active, Port D is asynchronously readable and writable through the chip Select (RE2/CS), Read (RE0/RD), and Write (RE1/WR) control inputs.

At this time, not many general-purpose applications for the PSP port have been documented, outside of its use as a multi-microprocessor interface. For this reason we have excluded PSP programming from this context.

14.3 PIC “Free-style” Serial Programming

This section is about PIC serial programming and circuit design that does not follow any specific communications protocol. In this sense, we have used the expression “free-style” as opposed to circuits and programs constrained by the requirements of a standard or convention. Many self-contained PIC circuits that do not interface with standardized components can benefit from not having to follow any specific standard. Later in this chapter, and in other chapters in the book, we present examples of PIC circuits and programs that follow established communications protocols. The titles of

352

Chapter 14

the corresponding sections refer to the specific standards or protocols; for example, the section titled PIC RS-232-C Serial Programming found in this chapter.

The advantages of so-called “free-style” circuit design and programming are greater in ease in development and the use of fewer hardware components. When designer and programmer are not constrained by the specifications of a standard, the circuit can be implemented with a minimal number of hardware components. By the same token, software is simpler and easier to develop.

The following examples of free-style communications systems are presented in the sections that follow:

1.A PIC to PIC communications circuit and program. Two programs are required: one for the receiver PIC and one for the sender.

2.Serial-to-parallel and parallel-to-serial circuit and program. Circuit uses 74HC164 and

74HC165 ICs.

14.3.1 PIC-to-PIC Serial Communications

Perhaps the most obvious and straightforward mode of PIC serial communications is one that takes place between two PICs. In this case, one PIC acts as a sender, or master, and the other one as a receiver or slave, although it is also possible for sender and receiver to exchange roles. Consider a circuit in which one PIC polls the state of a bank of switches and then sends the result serially to a second PIC that controls a bank of LEDs to be lighted according to the switch settings. The reason for this circuit is that some PICs may not have a sufficient number of ports to monitor eight switches and control eight LEDs.

PIC-to-PIC Serial Communications Circuits

Actually, the system required for one PIC reading data and serially sending the result to another PIC that outputs the data can be visualized as two separate circuits. One circuit is used to read the state of the eight DIP switches and to send the data serially to another PIC circuit that displays the results. Figure 14-7 shows the two PIC-based circuits.

Structurally, the circuits in Figure 14-7 are quite similar to ones described previously in this book. The bottom circuit contains eight DIP switches wired to ports RB0 to RB7. A pushbutton switch is wired to port RA2 and a LED to port RA3. The serial output is through port RA1. The circuit at the top of Figure 14-7 has eight LEDs wired to ports RB0 to RB7. There is a pushbutton on port RA2 and a LED on port RA3. Input into the circuit is through port RA0. In the remainder of this description we refer to the bottom circuit as the sender circuit and PIC and the one on the top as the receiver circuit and PIC.

The pushbuttons are necessary so that sender and receiver are synchronized. In operation, the receiver circuit is first activated by pressing the switch labeled “receive ready.” The LED on the top circuit lights to indicate the ready state. The sender circuit has a LED labeled “ready” that indicates its state. The user presses the switch labeled “send ready” in the sender circuit. At that time, the program in the sender reads the state of the DIP switches and sends the data out, one bit at a time, through the line labeled “serial out” in the diagram. The receiver reads the eight bits in its “serial in” line and lights the LEDs accordingly.

Communications

353

R=470 Ohm

RECEIVE

READY

LED

RESET

+5V

R=10K

RECEIVE

READY

SERIAL

IN

+5V

R=10K

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

1

 

16F84

18

 

 

 

 

 

 

 

 

Osc

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

RA2

RA1

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

2

 

RA3

RA0

 

17

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

3

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

16

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

4

 

RA4/TOCKI

OSC1

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

MCLR

OSC2

 

 

15

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

5

 

 

 

 

 

 

 

 

 

 

14

 

 

 

+5V

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Vss

Vdd

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

6

 

 

 

 

 

 

 

 

 

 

13

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

RB0/INT

RB7

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

7

 

 

 

 

 

 

 

 

 

 

12

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

8

 

RB1

RB6

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

11

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

RB2

RB5

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

9

 

 

 

 

 

 

 

 

 

 

10

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

RB3

RB4

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

R=470Xx8 Ohm

R=470 Ohm

SEND

READY

LED

RESET

+5V

R=10K

SEND

SERIAL

OUT

+5V

R=10K

1

16F84

 

18

Osc

 

RA2

RA1

 

 

2

 

17

 

RA3

RA0

 

 

3

 

16

 

RA4/TOCKI

OSC1

 

 

4

 

15

 

MCLR

OSC2

 

 

5

 

14

+5V

Vss

Vdd

 

6

 

13

 

RB0/INT

RB7

 

 

7

 

12

 

RB1

RB6

 

 

8

 

11

 

RB2

RB5

 

 

9

 

10

10K R

RB3

RB4

 

 

 

 

X 8

 

 

 

DIP SW

 

 

 

(DATA)

Figure 14-7 PIC-to-PIC Serial Communications Circuits

354

Chapter 14

PIC-to-PIC Serial Communications Programs

The software consists of two different programs, one to run in the sender PIC and one in the receiver PIC. Asynchronous communications require that sender and receiver operate at the same data speed. Both devices need not run at the same clock speed, but both must synchronize data transmission and reception at the same clock rate. Since the easiest way to accomplish this is to have both PICs use the same oscillator at the same speed, we make this assumption in the programs that follow.

The instruction time and clock rate of a PIC are one-fourth of its clock speed. Thus, a PIC with a 4Mhz clock runs at 1,000,000 cycles per second, and the default timer speed is:

1,000,000 = μ 3,906.25 s. per bit

256

approximately 3,906µs per clock cycle. Although 3,906µs is not a standard baud rate, the present application is self-contained, therefore there is no need to conform to

RS232-C or any other protocol.

Since it seems more intuitive to associate a high voltage with a logic 1 and a low voltage with a logic 0, we will adopt this convention in the present application. Nevertheless, we will borrow the character structure from the RS-232-C convention, that is, information will contain a start bit, a series of eight data bits, and a stop bit.

No parity is implemented. Figure 14-8 shows the bit structure for one character in our application.

START BIT

 

 

 

 

DATA BITS (10010001 = 0x91)

 

 

 

 

STOP BIT

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

0

 

1

0

0

1

0

0

1

0

 

1

 

 

 

LOGIC ONE STATE

Signal

Edge of

start bit

Protocol (in this example): 1 start bit

8 data bits (character) no parity bit

1 stop bit

Figure 14-8 Data Structure for PIC-to-PIC Application

Communications

355

The sender program, named SerialSnd, performs the following initialization operations:

1.Line RA2 is initialized for input since the pushbutton switch is located on this line. Lines RB0 to RB7 are also input, since they are connected to the DIP switch array.

2.The prescaler is assigned to the Watchdog Timer so that channel TMR0 runs at full processor speed.

3.Interrupts are disabled.

Initialization code is as follows:

; Port-A, bit 2 is input. All others are output

movlw

b’00000100’

; Port-A bit 2 is input

 

 

; all others are output

tris

porta

 

; Port-B is all input

 

movlw

b’11111111’

 

tris

portb

 

bsf

porta,1

;Marking bit

;Prepare to set prescaler clrf tmr0 clrwdt

;Setup OPTION register for full timer speed

 

 

 

movlw

 

b’11011000’

 

 

;

1

1

0

1

1

0 0 0 <= OPTION bits

 

 

;

|

|

|

|

|

|__|__|_____

PS2-PS0 (prescaler bits)

;

|

|

|

|

|

 

Values for Timer0

 

;

|

|

|

|

|

 

*000

= 1:2

001 =

1:4

;

|

|

|

|

|

 

010

= 1:8

011 =

1:16

;

|

|

|

|

|

 

100

= 1:32

101 =

1:64

;

|

|

|

|

|

 

110

= 1:128 111 =

1:256

;

|

|

|

|

|______________

PSA

(prescaler assign)

;

|

|

|

|

 

 

*1

=

to WDT

 

 

;

|

|

|

|

 

 

0

=

to Timer0

 

;

|

|

|

|_________________

TOSE (Timer0 edge

select)

;

|

|

|

 

 

 

0

=

increment on low-to-high

;

|

|

|

 

 

 

*1

=

increment in high-to-low

;

|

|

|____________________

TOCS (TMR0 clock source)

;

|

|

 

 

 

 

*0

=

internal clock

 

;

|

|

 

 

 

 

1

=

RA4/TOCKI bit

source

;

|

|_______________________

INTEDG (Edge select)

;

|

 

 

 

 

 

0

=

falling edge

 

;

|

 

 

 

 

 

*1

=

raising edge

 

;|__________________________ RBPU pullups

;

 

0

=

enabled

;

 

*1

=

disabled

option

 

 

 

 

; Disable interrupts

 

 

 

bcf

intcon,5

; Timer0 overflow disabled

356

 

Chapter 14

bcf

intcon,7

; Global interupts disabled

Once initialized, the program performs the following functions:

1.The SEND READY LED is turned on.

2.Code monitors the SEND pushbutton switch.

3.Once the switch is pressed, the program turns off the SEND READY LED.

4.The state of the DIP switches is obtained by reading RB0 to RB7.

5.The byte from Port-B is sent through the serial line.

The following code fragment shows the procedure to send serial data.

;============================================================

;

procedure to send serial data

;============================================================

;ON ENTRY:

;local variable dataReg holds 8-bit value to be

;transmitted through port labeled serialLN

;OPERATION:

;1. The timer at register TMR0 is set to run at

;maximum clock speed, that is, 256 clock beats.

;The timer overflow flag in the INTCON register

;is set when the timer cycles from 0xff to 0x00.

;2. Each bit (start, data, and stop bits) is sent

;at a rate of 256 timer beats. That is, each bit is

;held high or low for one full timer cycle (256

;clock beats).

;3. The procedure tests the timer overflow flag

;(tmrOVF) to determine when the timer cycle has

;ended, that is when 256 clock beats have passed.

;

sendData:

movlw

0x08

; Setup shift counter

movwf bitCount

;=======================

;send START bit ;=======================

;Set line low then hold for 256 timer clock beats.

bcf

PORTA,serialLN

; Send start bit

; First reset timer

 

clrf

TMR0

; Reset timer counter

bcf

INTCON,tmrOVF

; Reset TMR0 overflow flag

; Wait for 256 timer clock beats

 

startBit:

 

 

btfss

INTCON,tmrOVF

; timer overflow?

goto

startBit

; Wait until set

; At this point timer has cycled. Start bit has ended

bcf

INTCON,tmrOVF

; Clear overflow flag

Communications

357

;========================

;send 8 DATA bits ;========================

;Eight data bits are sent through the serial line

;starting with the high-order bit. The data byte is

;stored in the register named dataReg. The bits are

;rotated left to the carry flag. Code assumes the bit

;is zero and sets the serial line low. Then the carry

;flag is tested. If the carry is set the serial line

;is changed to high. The line is kept low or high for

;256 timer beats.

send8:

rlf

dataReg,f

; Bit into carry flag

bcf

PORTA,serialLN

; 0 to serial line

;Code can assume the bit is a zero and set the line

;low since, if low is the wrong state, it will only

;remain for two timer beats. The receiver will not

;check the line for data until 128 timer beats have

;elapsed, so the error will be harmless. In any case,

;there is no assurance that the previous line state is

;the correct one, so leaving the line in its previous

;state could also be wrong.

btfsc

STATUS,c

; Test carry flag

bsf

PORTA,serialLN

; Bit

is set. Fix error.

bitWait:

 

 

 

 

btfss

INTCON,tmrOVF

;

Timer cycled?

goto

bitWait

;

Not

yet

;At this point timer has cycled.

;Test for end of byte, if not, send next bit

bcf

INTCON,tmrOVF

; Clear overflow flag

decfsz

bitCount,f

;

Last bit?

goto

send8

;

not yet

;=========================

;hold MARKING state ;=========================

;All 8 data bits have been sent. The serial line must

;now be held high (MARKING) for one clock cycle

bsf

PORTA,serialLN

; Marking state

markWait:

 

 

 

btfss

INTCON,tmrOVF

;

Done?

goto

markWait

;

not yet

;=========================

; end of transmission

;=========================

return

358

Chapter 14

The code comments explain the routine’s operation.

The receiving program, named SerialRcv, runs in the receiver PIC. In this case, the serial line is RA0. Input from the sender program is received through this line. The program performs the following initialization operations:

1.Lines RA0 and RA2 are initialized for input since the pushbutton switch is located on RA2 and RA0 is the serial input line. Lines RB0 to RB7 are output since they are wired to the eight LEDs.

2.The prescaler is assigned to the Watchdog Timer so that channel TMR0 runs at full processor speed.

3.Interrupts are disabled.

Once initialized, code performs the following functions:

1.The SEND READY LED is turned on.

2.Code monitors the RECEIVE READY pushbutton switch.

3.Once the switch is pressed, the program turns on the RECEIVE READY LED.

4.Code then monitors the serial line for the first low that indicates the leading edge of the start bit.

5.Once the start bit is detected, code waits for 128 clock cycles to locate the center of the start bit. This synchronizes the receiver with the sender and accommodates small timing errors.

6.The eight data bits are then received and stored.

7.After waiting for the stop bit, code turns off the RECEIVE READY LED and sets the eight LEDs according to the data received through the serial line.

The following code fragment is the procedure rcvData from the SerialRcv program:

;============================================================

;

procedure to receive serial data

;============================================================

;ON ENTRY:

;local variable dataReg is used to store 8-bit value

;received through port (labeled serialLN)

;OPERATION:

;1. The timer at register TMR0 is set to run at

;maximum clock speed, that is, 256 clock beats.

;The timer overflow flag in the INTCON register

;is set when the timer cycles from 0xff to 0x00.

;2. When the START signal is received, the code

;waits for 128 timer beats so as to read data in

;the middle of the send period.

;3. Each bit (start, data, and stop bits) is read

;at intervals of 256 timer beats.

;4. The procedure tests the timer overflow flag

;(tmrOVF) to determine when the timer cycle has

Communications

359

; ended, that is when 256 clock beats have passed.

;=============================================================

rcvData:

clrf

TMR0

;

Reset timer

movlw

0x08

;

Initialize bit counter

movwf

bitCount

 

 

;=========================

; wait for START bit

;=========================

startWait:

 

 

btfsc

PORTA,0 ; Is port A0 low?

goto

startWait

; No. Wait for mark

;=========================

;offset 128 clock beats ;=========================

;At this point the receiver has found the falling

;edge of the start bit. It must now wait 128 timer

;beats to synchronize in the middle of the sender’s

;data rate, as follows:

;

|<=========

falling edge of START bit

;

|

 

 

;

|-----|<====== 128 clock beats offset

;

-----------.

|

.-------

;

|

 

| <== SIGNAL

;

 

-----------

 

;

|<---256--->|

;

 

 

 

 

movlw

0x80

; 128 clock beats offset

 

movwf

TMR0

; to TMR0 counter

 

bcf

INTCON,tmrOVF

; Clear overflow flag

offsetWait:

 

 

 

btfss

INTCON,tmrOVF

; Timer overflow?

 

goto

offsetWait

; Wait until

 

btfsc

PORTA,0

; Test start bit for error

 

goto

offsetWait

; Recycle if a false

start

 

 

 

;==========================

 

;

receive data

 

;==========================

 

 

clrf

TMR0

; Restart timer

 

bcf

INTCON,tmrOVF

; Clear overflow flag

; Wait for 256 timer cycles for first/next data bit

bitWait:

 

 

 

btfss

INTCON,tmrOVF

; Timer cycle end?

 

goto

bitWait

; Keep waiting

; Timer has counter 256 beats

 

 

bcf

INTCON,tmrOVF

; Reset overflow flag

 

movf

PORTA,w

; Read Port-A into w

360

 

 

 

Chapter 14

 

movwf

temp

; Store value read

 

rrf

temp,f

; Rotate bit 0 into carry flag

 

rlf

rcvReg,f ; Rotate carry into rcvReg bit 0

 

decfsz

bitCount,f

; 8 bits received

 

goto

bitWait

 

; Next bit

; Wait for one time cycle at end of reception

markWait:

 

 

 

 

btfss

INTCON,tmrOVF

; Timer overflow flag

 

goto

markWait

 

; keep waiting

;========================

 

 

;

end of reception

 

 

;========================

 

 

 

return

 

 

 

Neither the SerialRcv nor the SerialSnd programs contain any handshake signal. The programs rely on the user turning-on the receiver before the send function is activated. If this is not the case, the programs fail to communicate. But looking at the circuit diagram in Figure 14-7, we notice that there are available ports in both receiver and sender circuits. The circuit designer could interconnect two ports, one in the receiver and one in the sender, so as to provide a handshake signal.

For example, lines RA4 in both circuits can be interconnected. Then Port-A, line 4, in the sender circuit is defined as input and the same line as output in the receiver. The receiver could then set the handshake line high to indicate that it is ready to receive. The sender monitors this same port and does not start the transmission of each character until it reads that the handshake line is high. In this manner, the receiver can suspend transmission at any time and prevent data from being lost. At the same time, the “receiver ready” and “send ready” LEDs can be eliminated.

14.3.2 Program Using Shift Register ICs

The problem of handling multiple input and output lines, which was resolved in the previous example by using two PICs, can also be tackled by means of special-purpose integrated circuits. The term shift register refers to the fact that register input and output are connected in a way that data is shifted-down a set of flip-flops when the circuits are activated. Many variations of shift registers ICs are available, the most popular ones being serial-in to serial-out, parallel-in to parallel-out, serial-in to parallel-out, and parallel-in to serial-out. In shift register terminology the in and out terms refer to the function in the registers themselves, and are not related to the functions that these elements perform in a particular circuit. Figure 14-9 shows an input/output circuit using shift registers.

The circuit in Figure 14-9 shows the use of a parallel-to-serial IC (74HC165) that reads the state of eight input switches, and a serial-to-parallel IC (74HC164) that outputs data to eight LEDs. Without the shift register ICs, the circuit would require sixteen ports, more than those available in the 16F84. Using the shift registers, only six PIC ports are required, leaving eight ports available on the PIC. The demonstration program for the circuit in Figure 14-9 is named Serial6465.

Communications

361

RESET

+5V

R=10K

 

 

 

 

 

 

 

74HC164

 

 

 

 

 

 

 

 

 

 

 

+5V

R=10K

 

 

 

 

DI

Vcc

 

 

+5V

 

 

 

 

 

 

5V

7

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

6

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

0

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

5

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

1

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

24

3CLR

Vss CLK

R=470Xx8 Ohm

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

1

 

16F84

18

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

RA2

RA1

 

 

 

 

 

 

 

Osc

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

2

 

 

 

 

 

 

 

 

 

 

17

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

RA3

RA0

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

3

 

 

 

 

 

 

 

 

 

 

16

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

4

 

RA4/TOCKI

OSC1

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

MCLR

OSC2

 

 

 

 

15

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

5

 

Vss

Vdd

 

 

 

 

 

 

 

14

 

+5V

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

6

 

 

 

 

 

 

 

 

 

 

13

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

RB0/INT

RB7

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

7

 

 

 

 

 

 

 

 

 

 

12

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

RB1

RB6

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

8

 

 

 

 

 

 

 

 

 

 

11

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

RB2

RB5

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

9

 

 

 

 

 

 

 

 

 

 

10

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

RB3

RB4

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

+5V

74HC165

DIP SW

Load

Vcc

 

 

 

(DATA)

CLK0

Enab

 

4

3

 

5

2

 

6

1

 

7

0

10K R

 

 

X 8

!Hout

DI

 

Vss

Hout

 

Figure 14-9 Input/output Circuit using Shift Registers

The 74HC165 Parallel-to-Serial Shift Register

The 74HC165 (sometimes called the 165) is a parallel-in, serial-out high-speed 8-bit shift register. Shift registers are discussed in Section 6.4.7. Figure 14-10 (in the following page) shows the pin-out of the 74HC165.

362

 

Chapter 14

 

 

 

 

 

 

shift/load

clock

D4

D5

D6

D7

serial output

GND

1

 

16

+5V

2

 

15

clock inhibit

3

 

14

D3

4

 

13

D2

 

74HC165

 

D1

5

 

12

6

 

11

D0

7

 

10

serial input

8

 

9

serial output

 

 

 

 

Figure 14-10 74HC165 Pin-Out

In the 165, pins 3 to 6 and 11 to 14 (labeled D0 to D7) are used as parallel data input lines. Normally these pins are connected to input sources, such as switches or other two-state devices. Serial output takes place through pin number 9, labeled serial output Q. An inverted output is available at pin number 7. The shift/load control line, at pin number 1, is used to latch the data into the 165 shift registers. For example, assume that the 165’s input lines are connected to sources that can change state in time. These highs and lows are not recorded internally in the 165 until the shift/load line is pulsed. When this line is pulsed, line values are said to be latched. After the data lines are latched, the 165 clock-line is pulsed in order to sequentially shift-out each of the eight bits stored internally. Shifting takes place with the most significant bit first. The actual operations are as follows:

1.A local data storage register is cleared and a local counter is initialized for 8 data bits.

2.The 165 shift/load line is pulsed to reset the shift register.

3.The status of the serial output line (165 pin number 9) can now be read to determine the value of the bit shifted out.

4.The bit is stored in a data register and the bit counter is decremented. If the last bit was read the routine ends.

5.If not, the clock line is pulsed to shift-out the next bit. Execution continues at step number 3.

The wiring of the 165 normally requires at least three interface lines with the PIC. One line connects to the 165 serial output (pin number 9), another one to the clock line (pin number 2), and a third one to the shift/load line (pin number 1). The eight 165 data lines are normally wired to the input source.

Communications

363

The following code fragment lists a procedure to interface a 16F84 PIC with a 74HC165 parallel-to-serial shift register:

;============================================================

; constant definitions from wiring diagram

;============================================================

#define clk65LN 1

;|

— 74HC165 lines

#define loadLN 2

;|

 

.

 

 

.

 

 

.

 

 

;============================================================

;74HC165 procedure to read parallel data and send

;

serially to PIC

;============================================================

;OPERATION:

;1. Eight DIP switches are connected to the input

;ports of an 74HC165 IC. Its output line Hout,

;and its control lines CLK and load are connected

;to the PIC’s Port-B lines 0, 1, and 2

;respectively.

;2. Procedure sets a counter (bitCount) for 8

;iterations and clears a data holding register

;(dataReg).

;3. Port-B bits are read into w. Only the lsb of

;Port-B is relevant. Value is stored in a working

;register and the meaningful bit is rotated into

;the carry flag, then the carry flag bit is

;then shifted into the data register.

;4. The iteration counter is decremented. If this

;is the last iteration the routine ends. Otherwise

;the bitwise read-and-write operation is repeated.

in165:

 

 

clrf

dataReg

; Clear data register

movlw

0x08

; Initialize counter

movwf

bitCount

 

bcf

PORTB,loadLN

; Reset shift register

bsf

PORTB,loadLN

 

nextBit:

 

 

movf

PORTB,w

; Read Port-B (only LOB is

 

 

; meaningful in this routine)

movwf

workReg

; Store value in local

 

;register

 

rrf

workReg,f

; Rotate LOB bit into carry

 

 

; flag

rlf

dataReg,f

; Carry flag into dataReg

decfsz

bitCount,f

; Decrement bit counter

goto

shiftBits

; Continue if not zero

364

 

Chapter 14

Return

 

; done

shiftBits:

 

 

bsf

PORTB,clk65LN

; Pulse clock

bcf

PORTB,clk65LN

 

goto

nextBit

; Continue

The procedure in165 is in the program Serial6465 listed at the end of this chapter.

74HC164 Serial-to-Parallel Shift Register

The circuit in Figure 14-9 also uses a 74HC164 serial-to-parallel shift register for output to the eight LEDs. Figure 14-11 shows the pin-out of the 74HC164 IC.

input A

 

 

 

 

+5V

1

 

14

input B

2

 

13

Q7

Q0

3

 

12

Q6

Q1

4

74HC164

11

Q5

Q2

5

 

10

Q4

Q3

 

 

 

 

 

6

 

9

reset/clear

GND

7

 

8

clock

 

 

 

 

 

 

 

Figure 14-11 74HC164 Pin Out

Serial input into the 164 is through the input A line (pin number 1). Parallel output is through the lines labeled Q0 to Q7. The reset/clear line (on pin 9) and the clock line (on pin 8) provide the control functions. The operations are as follows:

1.A local data storage register holds the 8-bit value that serves as data input. A local counter is initialized for 8 data bits.

2.The 164 shift register is cleared by pulsing the reset/clear line.

3.The first/next bit of the data operand is placed on the input line.

4.Bit is shifted-in by pulsing the 164 clock line.

5.Bit counter is decremented. If it goes to zero the routine ends.

6.Otherwise, the bits in the source operand are shifted and execution continues at step number 3.

The following code fragment lists a procedure to interface a 16F84 PIC with a 74HC164 serial-to-parallel shift register:

;=====================================================

; constant definitions from wiring diagram

;=====================================================

#define clockLN 1

;|

Communications

 

365

#define clearLN 2

;|

— 74HC164 lines

#define dataLN 0

;|

 

...

 

 

;============================================================

;74HC164 procedure to send serial data ;============================================================

;ON ENTRY:

;local variable dataReg holds 8-bit value to be

;transmitted through port labeled serialLN

;OPERATION:

;1. A local counter (bitCount) is initialized to

;8 bits

;2. Code assumes that the first bit is zero by

;setting the data line low. Then the high-order

;bit in the data register (dataReg) is tested.

;If set, the data line is changed to high.

;3. Bits are shifted in by pulsing the 74HC164

;clock line (CLK).

;4. Data bits are then shifted left and the bit

;counter is tested. If all 8 bits have been sent

;the procedure returns.

out164:

 

 

; Clear 74HC164 shift register

 

bcf

PORTA,clearLN

; 74HC164 CLR clear low

bsf

PORTA,clearLN

; then high again

; Init counter

 

 

movlw

0x08

; Initialize bit counter

movwf

bitCount

 

sendBit:

 

 

bcf

PORTA,dataLN

; Set data line low (assume)

;Using this assumption is possible because the bit is not

;shifted in until the clock line is pulsed.

btfsc

dataReg,highBit

;

test number bit 7

 

bsf

PORTA,dataLN

;

Change assumption

if set

;=========================

;pulse clock line ;=========================

;Bits are shifted in by pulsing the 74HC164 CLK line

 

bsf

PORTA,clockLN

; CLK high

 

bcf

PORTA,clockLN

; CLK low

;=========================

 

; Rotate data bits left

 

;=========================

 

 

rlf

dataReg,f

; Shift left data bits

 

decfsz

bitCount,f

; Decrement bit counter

 

goto

sendBit

; Repeat if not 8 bits

;=========================

 

;

end of transmission