notTOIF:

retfie

One of the initial operations of the service routine is to clear the TOIF bit in the INTCON register. This action re-enables the timer interrupt and prevents counting cycles to be lost. Since the interrupt is generated every 256 beats of the timer, there is no risk that by enabling the timer interrupt flag a re-entrant interrupt will take place.

The interrupt-based timer program named LapseTmrInt can be tested on the same circuit shown in Figure 12-3.

12.4 The Watchdog Timer

The 16F84 contains an independent timer with its own clock source called the Watchdog Timer, or WDT. The Watchdog Timer provides a way for the processor to recover from a software error that impedes program continuation, such as an endless loop. The

Watchdog Timer is not designed to recover from hardware faults, such as a brown-out.

The Watchdog Timer hardware is independent of the PIC’s internal clock. Its time-out period lasts approximately 18ms to 2.3s, depending on whether the prescaler is used and on its setting. It is not very accurate due to its sensitivity to temperature. According to Microchip’s documentation, under worst-case conditions, its time-out period can take up to several seconds. The following program elements relate to Watchdog Timer operation:

1.Configuration bit 2, labeled WDTE, enables and disables the Watchdog Timer during system configuration. The WDT cannot be set or reset at runtime. It is enabled and disabled during programming.

2.The PSA bit in the OPTION register selects whether the prescaler is assigned to the

Watchdog Timer or to the Timer0 module.

3.Bits PS2 to PS0 in the OPTION register allow assigning eight rates to the Watchdog Timer, from 1:1 to 1:128.

4.Bit 4 of the STATUS register, named the TO bit, is cleared when a time-out condition occurred that originated in the WDT.

5.The power-down bit (PD) in the STATUS register is set after the execution of the clrwdt instruction.

6.The clrwdt instruction clears the Watchdog Timer. It also clears the prescaler count (if the prescaler is assigned to the Watchdog Timer) and sets STATUS bits TO and PD.

The WDT provides a recovery mechanism for software errors. When the WDT times-out, the TO flag in the STATUS register is cleared and the program counter is reset to 0000 so that the program restarts. Applications can prevent the reset by issuing the clrwdt instruction before the time-out period ends. When clrwdt executes the WDT time-out period restarts.

12.4.1 Watchdog Timer Programming

Not much information is available regarding the details of operation of the Watchdog Timer in the 16F84. Using the WDT in applications is not just a simple matter of restarting the counter with the clrwdt instruction. The timer is designed to detect software errors that can hang up a program, but how it detects these errors and which conditions trigger the WDT operation are not clear from the information provided by Microchip. For example, an application that contains a long delay loop may find that the Watchdog Timer forces an untimely break out of the loop. The Watchdog Timer provides a powerful error-recovery mechanism, but its use requires careful consideration of program conditions that could make the timer malfunction.

12.5 Sample Programs

The following programs demonstrate the programming discussed in this chapter.

12.5.1 The Tmr0Counter program

;File name: Tmr0Counter.asm

;Date: April 30, 2006

;Author: Julio Sanchez

;Processor: 16F84A

;Reference: SevenSeg Circuit and Board

;Description:

;Test program for the Timer0 counter. The program counts

;the number of presses of the pushbutton switch on port

;RA4/TOCKI and displays the count on a seven segment LED.

;Switch is wired active low.

;

; Switches used in __config directive:

;_PWRTE_OFF

;|

;|_____ * indicates set up values

;=========================

;set up and configuration ;=========================

main:

;Clear the timer and the watchdog clrf TMR0

clrwdt

;Set up the OPTION register bit map

; | |_______________________ INTEDG (Edge select)

;|__________________________ RBPU (Pullup enable)

;=================================

;Check value in TMR0 and display ;=================================

;Every press of the pushbutton switch connected to line

;RA4/TOCKI adds one to the value in the TMR0 register.

;Loop checks this value, adjusts to the range 0 to 15

;and displays the result in the seven-segment LED on

;Port-B

checkTmr0:

; Eliminate four high order bits

;At this point the w register contains a 4-bit value

;in the range 0 to 0xf. Use this value (in w) to

;obtain seven-segment display code

12.5.2 The Timer0 Program

;File: Timer0.ASM

;Date: April 27, 2006

;Author: Julio Sanchez

;Processor: a6F84A

;Description:

;Program to demonstrate programming of the 16F84A

;TIMER0 module. Program flashes eight LEDs in sequence

;counting from 0 to 0xff. Timer0 is used to delay

;the count.

;===========================

;switches ;===========================

;Switches used in __config directive:

;_PWRTE_OFF

error)

;|

;|_____ * indicates set up values

;=====================================================

; None in this application

;

;========================================================

;========================================================

goto main

;

;=============================

;interrupt handler ;=============================

org 0x08 ;=============================

;main program ;============================= main:

;Clear the Watchdog Timer and reset prescaler clrwdt

;Set up the OPTION register bit map

;|__________________________ RBPU (Pullup enable)

; Port-A is not used in this program mloop:

;******************************

;delay sub-routine

;uses Timer0 ;****************************** TM0delay:

;Initialize the timer register

;Routine tests the value in the TMR0 register by

;subtracting 0xff from the value in TMR0. The zero flag

;is set if TMR0 = 0xff

end

12.5.3 The LapseTimer Program

;File: LapseTimer.ASM

;Date: May 1, 2006

;Author: Julio Sanchez

;Processor: 16F84A

;Description:

;Using Timer0 to produce a variable-lapse delay.

;The delay is calculated based on the number of machine

;cycles necessary for the desired wait period. For

;example, a machine running at a 4 Mhz clock rate

;executes 1,000,000 instructions per second. In this

;case a 1/2 second delay requires 500,000 instructions.

;The wait period is passed to the delay routine in three

;program registers which hold the high-, middle-, and

;low-order bytes of the counter. ;===========================

;switches

;===========================

; Switches used in __config directive:

;_PWRTE_OFF

;|

;|_____ * indicates set up values

;========================================================

; m a i n p r o g r a m

;========================================================

;

;=============================

; interrupt handler

;=============================

org 0x04

;goto IntServ ;=============================

;main program ;============================= main:

;Clear the Watchdog Timer and reset prescaler clrf TMR0

clrwdt

;Set up the OPTION register bit map

;|__________________________ RBPU (Pullup enable)

;Port-A is not used in this program ;============================

;display loop ;============================ mloop:

;Turn on LED

; Re-initialize counter and delay call onehalfSec

call TM0delay goto mloop

;==================================

;variable-lapse delay procedure

;using Timer0 ;==================================

;ON ENTRY:

;Variables countL, countM, and countH hold

;the low-, middle-, and high-order bytes

;of the delay period, in timer units

;Routine logic:

;The prescaler is assigned to Timer0 and set up so

;that the timer runs at 1:2 rate. This means that

;every time the counter reaches 128 (0x80) a total

;of 256 machine cycles have elapsed. The value 0x80

;is detected by testing bit 7 of the counter

;register.

;Note:

;The Timer0 register provides the low-order level

;of the count. Since the counter counts up from zero,

;in order to ensure that the initial low-level delay

;count is correct the value 128 - (xx/2) must be calculated

;where xx is the value in the original countL register.

;First calculate xx/2 by bit shifting

;Routine tests timer overflow by testing bit 7 of

;the TMR0 register.

cycle:

;At this point TMR0 bit 7 is set

;Clear the bit

;Subtract 256 from beat counter by decrementing the

;mid-order byte

decfsz countM,f

zero

;At this point the mid-order byte has overflowed.

;High-order byte must be decremented.

decfsz countH,f goto cycle

; At this point the time cycle has elapsed return

;==============================

;set register variables for

;one-half second delay ;==============================

;Procedure to initialize local variables for a

;delay of one-half second on a 16F84 at 4 Mhz.

;Timer is set up for 500,000 clock beats as

;follows: 500,000 = 0x07 0xa1 0x20

;|

;|_____ * indicates set up values

;===================================================== ; variables in PIC RAM ;===================================================== ; Local variables

cblock 0x0d

countH countM countL old_w old_STATUS endc

;========================================================

; m a i n p r o g r a m

;========================================================

;=============================

;main program ;============================= main:

;Clear the Watchdog Timer and reset prescaler clrf TMR0

clrwdt

;Set up the OPTION register bit map

;|__________________________ RBPU (Pullup enable)

;Port-A is not used in this program ;============================

;set up interrupts ;============================

;Clear external interrupt flag (INTF = bit 1)

;Enable global interrupts (GIE = bit 7)

;Enable RB0 interrupt (inte = bit 4)

;do-nothing loop ;============================

;All work is performed by the interrupt handler mloop:

goto mloop ;==============================

;set register variables for

;one-half second delay ;==============================

;Procedure to initialize local variables for a

;delay of one-half second on a 16F84 at 4 Mhz.

;Timer is set up for 500,000 clock beats as

;follows: 500,000 = 0x07 0xa1 0x20

;500,000 = 0x07 0xa1 0x20

;—— —— ——

movlw 0x07 movwf countH movlw 0xa1 movwf countM movlw 0x20 movwf countL

;The Timer0 register provides the low-order level

;of the count. Since the counter counts up from zero,

;in order to ensure that the initial low-level delay

;count is correct the value 256 - xx must be calculated

;where xx is the value in the original countL register.

sublw d’255’

; Now w has adjusted result. Store in TMR0

movwf TMR0

return

;=======================================================

;Interrupt Service Routine ;=======================================================

;Service routine receives control when the timer

;register TMR0 overflows, that is, when 256 timer beats

;have elapsed

IntServ:

; First test if source is a Timer0 interrupt

; If so clear the timer interrupt flag so that count continues

;=========================

;interrupt action ;=========================

;Subtract 256 from beat counter by decrementing the

;mid-order byte

decfsz countM,f

zero

;At this point the mid-order byte has overflowed.

;High-order byte must be decremented.

decfsz countH,f

goto exitISR

;At this point count has expired so the programmed time

;has elapsed. Service routine turns the LED on line 0,

;Port-B on and off at every conclusion of the count.

;This is done by xoring a mask with a one-bit at the

;Port-B line 0 position

movlw b’00000001’

xorwf PORTB,f

; Reset one-half second counter call onehalfSec

;=========================

;exit ISR ;========================= exitISR:

;Restore context

; Reset,interrupt notTOIF:

retfie

end