the delay ends. Since the counter is interrupt-driven, the processor continues to do other work in the foreground.

An even more ingenious option proposed by Black is a background counter that does not rely on interrupts. This is accomplished by introducing a 1:2 delay in the timer by means of the prescaler. Since now the timer beats at one-half the instruction rate, 128 timer cycles are required for one complete iteration at the full instruction rate. By testing the high-order bit of the timer counter, the routine detects when the count reaches 128. At that time the mid-range and high-range counter variables are updated (as in the non-interrupt version of the software described in the previous paragraph). The high-order bit of the timer is then cleared, but the low-order bits are not changed. This allows the timer counter not to lose step in the count, which remains valid until the next time the high-order bit is again set. During the period between the updating of the 3-byte counter and the next polling of the timer register, the program continues to perform other tasks.

Many of the details of the Black-Ammerman method are missing in our description. The reader should refer to the Internet article for a thorough coverage of this algorithm.

12.2 Timer0 as a Counter

In Section 12.0.1, we saw that Timer0 operation can be assigned to the PIC’s RA4/TOCKI pin by setting bit 5 of the OPTION register (labeled TOCS). This mode is referred to as the counter mode. When the timer is set up to work as a counter, then bit 4 of the OPTION register (labeled TOSE) allows selecting whether the counter increments on the high-to-low or low-to-high transition of the signal.

When an external clock input is present in the RA4/TOCKI pin, it must meet certain requirements. Used for Timer0, these requirements ensure that the external source can be synchronized with the internal phase clock. When no prescaler is used, the external clock input must be high and low for at least twice the internal clock rate. In addition, there must be a resistor-capacitor induced delay of 20 ns on both the high and the low cycles.

When a prescaler is used, the external clock input must be high and low for at least four times the rate of the internal clock rate. In addition, there must be a resis- tor-capacitor induced delay of 40 ns on both the high and the low cycles.

Once the counter mode is enabled, any pulse on pin RA4/TOCKI is automatically counted in the TMR0 register. The mechanism can be compared to an automatic interrupt since no program action is required to keep track of the number of pulses. The routine can be coded so that when the timer count overflows, an interrupt is generated. The interrupt handler then increments a supplementary counter so that events that exceed 256 pulses are recorded. The program named Tmr0Counter developed later in this chapter and contained in the book’s online software is an example of using the counter function of the Timer0 module.

12.3 Timer0 Programming

Software routines that use the Timer0 module range in complexity from simple approximate delay loops to configurable, interrupt-driven counters that must meet very high timing accuracy requirements. When the time period to be measured does not exceed the one obtained with the prescaler and the timer register count, then the coding is straightforward and the processing is uncomplicated. But often this is not the case. The following elements should be examined before attempting to design and code a Timer0-based routine:

1.What is the required accuracy of the timer delay?

2.Can the prescaler be used or is the prescaler devoted to the Watchdog Timer?

3.Does the program suspend execution while the delay is in progress, or does the application continue executing in the foreground?

4.Can the timer be interrupt-driven or must it be polled?

5.Will the delay be the same on all calls to the timer routine, or must the routine provide delays of different magnitude?

6.How long must the delay last?

In this section we explore several timer routines of different complexity and requirements. The first one uses the Timer0 module as a counter, as described in Section 12.2. Later, we develop a simple delay loop that uses the Timer0 register instead of an instruction count. We conclude with an interrupt-driven timer routine that can be changed to implement different delays.

12.3.1 Programming a Counter

The 16F84 can be programmed so that port RA4/TOCKI is used to count events or pulses by initializing the Timer0 module as a counter. Without interrupts, the process requires the following preparatory steps:

1.Port-A, line 4, (RA4/TOCKI) is defined for input.

2.The Timer0 register (TMR0) is cleared.

3.The Watchdog Timer internal register is cleared by means of the clrwdt instruction.

4.The OPTION register bits PSA and PSO:PS2 are initialized if the prescaler is to be used.

5.The OPTION register bit TOSE is set so as to increment the count on the high-to-low transition of the port pin if the port source is active low. Otherwise the bit is cleared.

6.The OPTION register bit TOCS is set to select action on the RA4/TOCKI pin.

Once the timer is set up as a counter, any pulse received on the RA4/TOCKI pin that meets the restrictions mentioned in Section 12.2 is counted in the TMR0 register. Software can read and write to the TMR0 register, located at address 0x01 in bank 0, in order to obtain or change the event count. If the timer interrupt is enabled when the timer is defined as a counter, the interrupt takes place every time the counter overflows, that is, when the count cycles from 0xff to 0x00.

;|__________________________ RBPU (Pullup enable)

Once the hardware is initialized, program operation consists of reading the value stored in TMR0, scaling this value to the display range 0 to 15, and displaying it on the seven-segment LED. Processing is as follows:

;=================================

;Check value in TMR0 and display ;=================================

;Every press of the pushbutton switch connected to line

;RA4/TOCKI adds one to the value in the TMR0 register.

;Loop checks this value, adjusts to the range 0 to 15

;and displays the result in the seven-segment LED on

;Port-B

;

checkTmr0:

; Eliminate four high order bits

;At this point the w register contains a 4-bit value

;in the range 0 to 0xf. Use this value (in w) to

;obtain seven-segment display code

;

;================================

;routine to return 7-segment

;codes ;================================ segment:

The programming of seven-segment LEDs was discussed in Chapter 10.

12.3.2 Timer0 as a Simple Delay Timer

Perhaps the simplest use of the Timer0 module is to implement a delay loop. In this application, the Timer0 module is initialized to use the internal clock by setting the TOSE bit of the OPTION register. If the prescaler is to be used, as is most likely, the PSA bit is cleared and the desired prescaling is entered in bits PS2 to PS0 of the OPTION register. The circuit in Figure 12-3 allows testing several timer-related programs developed in this chapter.

The program named Timer0, in the book’s online software package, uses a timer-based delay loop to flash in sequence eight LEDs that display the binary values from 0x00 to 0xff. The delay routine executes in the foreground, so that processing is suspended while the count is in progress. The initialization requires clearing the TOCS bit in the OPTION register to select the internal clock. The prescaler is assigned to Timer0 by clearing the PSA bit and bits PS2 to PS0 are set to assign a 1:256 prescale to the timer. The following code fragment shows the processing.

6

RB0/INT RB7

7

RB1 RB6

8

RB2 RB5

9

RB3 RB4

R=330x8 Ohm

Figure 12-3 Circuit for Testing Several Timer Programs

main:

;Clear the Watchdog Timer and reset prescaler clrwdt

;Set up the OPTION register

;|__________________________ RBPU (Pullup enable)

The delay procedure named TM0delay provides the necessary time lapse between successive increments in the count displayed. The code is as follows:

;******************************

;delay sub-routine

;uses Timer0 ;****************************** TM0delay:

;Initialize the timer register

;Routine tests the value in the TMR0 register by

;subtracting 0xff from the value in TMR0. The zero flag

;is set if TMR0 = 0xff

12.3.3 Measured Time Lapse

A variable time-lapse routine that can be edited or adjusted to produce delays within a specific time range is a useful tool in any programmer’s library. In previous sections, we developed delay routines that do so by counting timer pulses. This same idea can be used to develop a routine that produces accurate delays within a range.

The routine can be implemented to varying degrees of sophistication. One extreme would be a procedure that receives the desired time lapse as a parameter. Another option would be a procedure that reads the desired time lapse from program constants. In the program named LapseTimer contained in the book’s online software we develop a procedure in which the calling code passes the desired time delay in three variables containing the number of machine cycles necessary for the desired wait period. By using machine cycles instead of time units (such as microseconds or milliseconds), the procedure becomes easily adaptable to devices running at different clock speeds. Since each instruction requires four clock cycles, the device’s clock speed in Hz is divided by four in order to determine the number of machine cycles per time unit.

For example, a processor equipped with an 8 Mhz clock executes at a rate of

8,000,000/4 machine cycles per second; that is, 2,000,000 instruction cycles per second. To produce a one-quarter second delay requires a wait period of 2,000,000/4 or 500,000 instruction cycles. By the same token, the 16F84 running at 4 Mhz executes 1,000,000 instructions per second. In this case a one-quarter second delay would require waiting 250,000 instruction cycles.

The program titled lapseTimer in the book’s online software package uses Timer0 to produce a variable-lapse delay. The delay is calculated based on the number of machine cycles necessary for the desired wait period, as described in the preceding paragraph. The program uses the Black-Ammerman methods, which require a prescaler of 1:2 so that each timer iteration takes place at one-half the clock rate. The program initializes the OPTION register and the ports as follows:

main:

;Clear the Watchdog Timer and reset prescaler clrf tmr0

clrwdt

;Set up the OPTION regiser bit map

;|__________________________ RBPU (Pullup enable)

; Port-A is not used in this program

The LapseTimer program is designed to produce a one-half second delay on a 16F84 running at 4 Mhz; therefore, the delay requires 500,000 clock beats. The value is converted to hexadecimal and stored in a 3-byte counter, as follows:

500,000 = 0x07a120 or

countL = 0x20

countM = 0xa1

countH = 0x07

The variables countL, countM, and countH are defined locally and initialized by a procedure named onehalfSec, as follows:

;Procedure to initialize local variables for a

;delay of one-half second on a 16F84 at 4 Mhz.

;Timer is set up for 500,000 clock beats as

;follows: 500,000 = 0x07 0xa1 0x20

;500,000 = 0x07 0xa1 0x20

;—— —— ——

The delay routine uses the Timer0 register to provide the low-order level of the count. Since the counter counts up from zero to ensure that the initial low-level delay count is correct—the value 128 - (xx/2) must be calculated, where xx is the value in the original countL register. The program performs the division by 2 by shifting bits to the right by one position. The resulting value is subtracted from 128 and the result stored in TMR0, as follows:

The delay routine detects timer overflow by testing bit 7 of the TMR0 register. If the bit is set, then 256 time cycles have elapsed and the mid-order counter register is decremented. If the mid-order register underflows when it is decremented, then the high-order register is decremented. If it underflows, the counter has gone to zero and the delay routine ends. Processing is as follows:

cycle:

;

;At this point TMR0 bit 7 is set

;Clear the bit

;Subtract 256 from beat counter by decrementing the

;mid-order byte

;

decfsz countM,f

;At this point the mid-order byte has overflowed.

;High-order byte must be decremented.

decfsz countH,f

goto cycle

; At this point the time cycle has elapsed

return

The circuit in Figure 12-3 can be used to test the lapseTimer program.

Interrupt-driven Timer

Interrupt-driven timers and counters have several advantages over polled routines: first, the time lapse counting takes place in the background so that the application can continue to do other work in the foreground. Another advantage of an interrupt-driven counter is that the prescaler is unnecessary and can be used for the Watchdog Timer. Developing a timer routine that is interrupt-driven presents no additional challenges over the conventional interrupt-driven examples covered in Chapter 11. The initialization consists of configuring the OPTION and the INTCON register bits for the task at hand. In the particular case of an interrupt-driven timer, the following are necessary:

1.The external interrupt flag (INTF in the INTCON Register) must be initially cleared.

2.Global interrupts must be enabled by setting the GIE bit in the INTCON Register.

3.The Timer0 overflow interrupt must be enabled by setting the TOIE bit in the INTCON register.

In this example program, named LapseTmrInt, the prescaler is not used with the timer, so the initialization code sets the PSA bit in the OPTION register and the prescaler is assigned to the Watchdog Timer. The following code fragment is from the LapseTmrInt program:

main:

;Clear the Watchdog Timer and reset prescaler clrf tmr0

clrwdt

;Set up the OPTION register bit map

;|__________________________ RBPU (Pullup enable)

;Port-A is not used in this program ;============================

;set up interrupts ;============================

;Clear external interrupt flag (intf = bit 1)

;Enable global interrupts (gie = bit 7)

;Enable RB0 interrupt (inte = bit 4)

As in the program LapseTimer, developed previously in this chapter, the timer operates by decrementing a 3-byte counter that holds the number of timer beats required for the programmed delay. In the case of the LapseTmrInt program, the routine that initializes the register variables for a one-half second delay also correctly adjusts the initial value loaded into the TMR0 register. The code is as follows:

;==============================

;set register variables for

;one-half second delay ;==============================

;Procedure to initialize local variables for a delay of

;one-half second on a 16F84 at 4 Mhz. Timer is set up for a

;500,000 clock beats as follows: 500,000 = 0x07 0xa1 0x20

;500,000 = 0x07 0xa1 0x20

;—— —— ——

movlw 0x07 movwf countH movlw 0xa1 movwf countM movlw 0x20 movwf countL

;The TMR0 register provides the low-order level of

;the count. Since the counter counts up from zero,

;in order to ensure that the initial low-level delay

;count is correct, the value 256 - xx must be calculated

;where xx is the value in the original countL variable.

sublw d’256’

; Now w has adjusted result. Store in TMR0

movwf tmr0

return

The interrupt service routine in the LapseTmrInt program receives control when the TMR0 register underflows, that is, when the count goes from 0xff to 0x00. The service routine then proceeds to decrement the mid-range counter register and adjust, if necessary, the high-order counter. If the count goes to zero, the handler toggles the LED on Port-B, line 0, and re-initializes the counter variables by calling the onehalfSec procedure described previously. The interrupt handler is coded as follows:

;=======================================================

;Interrupt Service Routine ;=======================================================

;Service routine receives control when there the timer

;register TMR0 overflows, that is, when 256 timer beats

;have elapsed

IntServ:

; First test if source is a Timer0 interrupt

; If so clear the timer interrupt flag so that count continues

;=========================

;interrupt action ;=========================

;Subtract 256 from beat counter by decrementing the

;mid-order byte

decfsz countM,f

; zero

;At this point the mid-order byte has overflowed.

;High-order byte must be decremented.

decfsz countH,f

goto exitISR

;At this point count has expired so the programmed time

;has elapsed. Service routine turns the LED on line 0,

;Port-B on and off at every conclusion of the count.

;This is done by XORing a mask with a one-bit at the

;Port-B line 0 position

movlw b’00000001’

xorwf portb,f

; Reset one-half second counter call onehalfSec

;=========================

;exit ISR ;========================= exitISR:

;Restore context

; Return from interrupt