Interrupts

bit 7 GIE: Global Interrupt Enable bit

Figure 11-1 INTCON Register Bitmap

11.0.2 The OPTION Register

The OPTION Register is a readable and writeable register that contains controls for configuring the prescaler bits and assigning them to either TIMER0 or the Watchdog Timer, for selecting the increment mode on the RA4/TOCKI pin, the TIMER0 source clock, the rising or falling edge in the RB0 interrupt, and for enabling and disabling the internal Port-B’s pull-up resistors. The OPTION register is located in Bank1, at address 0x81. Although this register is not directly related to interrupts, several of its bits are related to the various interrupts. Figure 11-2 is a bitmap of the OPTION register.

Figure 11-2 OPTION Register Bitmap

11.1 Interrupt Sources

The 16F8X supports four different sources of interrupt:

1.External interrupt detected by line 0 of Port-B

2.Interrupts that originate in the timer (TMR0 overflow interrupt)

3.Interrupts that originate in changes of lines RB7 to RB4 in Port-B

4.EEPROM complete data write interrupt

11.1.1 Port-B External Interrupt

This external interrupt is triggered by either the rising or falling signal edge on port-B, line 0. Whether it is the rising or the falling edge of the signal depends on the setting of the INTEDG bit of the OPTION register.

The Port-B interrupt is useful in detecting and responding to external events; for example, in measuring the frequency of a signal or in responding with some PIC action to a change in the state of a hardware device. This interrupt can be disabled by clearing the corresponding bit in the INTCON register. If enabled, once the interrupt takes place, code must clear the corresponding flag bit before re-enabling the interrupt.

Suppose there is a circuit that contains an emergency switch that is activated by some critical event. One possible approach is to check the state of the switch by continuously polling the port to which it is wired. But in a complex program it may be difficult to ensure that the switch polling routine is called with sufficient frequency so that an emergency event is detected immediately. A more effective solution is to connect the emergency switch to line number 0 of Port-B and set up the Port-B external interrupt source. Now, whenever the emergency switch is activated, the program immediately responds via the interrupt mechanism. Furthermore, once the interrupt code has been developed and debugged it continues to function correctly no matter what changes are made to the rest of the program.

11.1.2 Timer0 Interrupt

The 16F84 is equipped with a special timer module, named Timer0, which serves both as a timer and as a counter. The Timer0 module, which is discussed in greater detail in Chapter 12, consists of an 8-bit readable register operated by an internal or external clock and attached to an 8-bit programmable prescaler. The prescaler is used to delay the timer by dividing the previous clock signal. The timer0 module can be set up to interrupt on overflow. In this case, an interrupt is generated whenever the counter goes from 0xff to 0x00.

The Timer0 counter interrupt can be used to measure events and to respond to elapsed periods. For example, the timer is used to measure events by determining the number of timer interrupts that have taken place since an event occurred. The timer of each interrupt is determined from the processor clock speed and the prescaler set up. The event time is calculated by multiplying the time of each interrupt by the number of interrupts that have occurred. In this case, the interrupt routine increments a counter register that is accessible to code anywhere in the program; so the actual count can be reset from inside or outside the service routine.

In responding to an elapsed period, the Timer0 interrupt service routine not only keeps track of the time elapsed since the event, but also tests for a certain counter value that represents the desired time limit. Once the timer counter reaches this pre-set limit, the service routine responds directly with the required action.

One powerful and common application of a Timer0 interrupt is in implementing serial communications. In this case, the timer interrupt is set up to take place at the baud rate at which the serial line is polled for data or at which individual data bits are sent. The sample program LapseTmrInt, developed in Chapter 12, demonstrates this use of the timer interrupt.

11.1.3 Port-B Line Change Interrupt

The third 16F84 interrupt source relates to a change in the values stored in Port-B lines 4 to 7. When this interrupt is enabled, any change in status in any of the four Port-B pins labeled RB7, RB6, RB5, and RB4 can trigger an interrupt. The interrupt is set up to take place when their status changes from logic one to logic zero, or vice versa. For this interrupt to take place, Port-B pins 4 to 7 must be defined as input. Otherwise, the interrupt does not take place.

The Port-B line-change interrupt provides a mechanism for monitoring up to four different interrupt sources, typically originating in hardware devices. When the interrupt is enabled, the current state of the Port-B lines is constantly compared to the old values. If there is a change in state in any of the four lines the interrupt is generated.

Implementation of the line change interrupt is not without complications. The characteristics of the external signal are necessary to develop code that correctly handles the various possible sources. Two pieces of information that are necessary in this case are:

1.The signal’s rising and falling edges

2.The pulse width of the interrupt trigger

The signal’s rising and falling edges determine the service routine’s entry point. For example, if the device is an active-low pushbutton switch, an interrupt typically is desired on the signal’s falling edge, that is, when it goes from high-to-low.

Knowledge about the signal’s width determines the processing required by the service routine. This is due to the fact that both the rising and the falling edge of the signal can trigger the interrupt. So, if the triggering signal has a small pulse width compared to the time of execution of the interrupt handler, then the interrupt line has returned to the inactive state before the service routine completes and a possible false interrupt on the signal’s falling edge is not possible. On the other hand, if the pulse width of the interrupt signal is large and the service routine completes before the signal returns to the inactive state, then the signal’s falling edge can trigger a false interrupt. Figure 11-3 (in the following page) shows both situations.

In the context of Figure 11-3, the period between the edge that triggers the interrupt and the termination of the interrupt handler is called the mismatch period. The mismatch period terminates when the service routine completes and the corresponding interrupt is re-enabled. If this happens after the interrupt signal is reset, no possible false interrupt takes place and no special provision is required in the handler. In fact, the interrupt handler runs correctly as long as the service routine takes longer to execute than the interrupt frequency. However, if the handler termi-

nates before the signal returns to its original state, then the handler must make special provisions to handle a possible false interrupt. In order to do this, the handler must first determine if the interrupt took place on the rising or the falling signal edge, which can be done by examining the corresponding port-B line. For example, if the interrupt is to take place on the rising edge only, and the line is low, then it can be ignored since it takes place on the falling edge.

CASE 1: relatively small pulse width

CASE 2: relatively large pulse width

Signal

Falling edge can trigger Raising edge false interrupt

triggers interrupt

Service routine complete Interrupt handler Interrupt flag cleared

in progress

Figure 11-3 Signal Pulse Width and Interrupt Latency

When an interrupt can take place on either the rising or the falling edge of the triggering signal, the interrupt source must have a minimum pulse width in order to ensure that both edges are detected. In this case, the minimum pulse width is the maximum time from the edge that triggered the interrupt to the moment when the interrupt flag is cleared. Otherwise, the interrupt is lost since the interrupt mechanism is disabled at the time it takes place.

The preceding discussion leads directly to the possibility of an interrupt taking place while the service routine of a previous interrupt is still in progress. These are called reentrant or nested interrupts. Several things must happen to allow reentrant interrupts. One of them is that interrupts must be re-enabled before the handler terminates. In addition, the service routine must be able to create different instances of the variables in use, usually allocated in the stack. The lack of a pro- gram-accessible stack and the PIC interrupt mechanism itself forces the conclusion that reentrant interrupts should not be attempted in PIC programs.