Total = 368 bytes

8.4.3 Indirect Addressing

The instruction set of most processors, including the PICs, provides a mechanism for accessing memory operands indirectly. Indirect addressing is based on the following capabilities:

1.The address of a memory operand is loaded into a register. This register is called the pointer.

2.The pointer register is then used to indirectly access the memory location at the address it “points to.”

3.The value in the pointer register can be modified (usually incremented or decremented) so as to allow access to other memory operands.

In the PIC architecture indirect addressing is implemented using two registers: INDF and FSR. The INDF register, always located at memory address 0x00 and mirrored in all banks, is not a physical register, in the sense that it cannot be directly accessed by code. The FSR register is the pointer register that is initialized to the address of a memory operand. Once a memory address is placed in FSR, any action on the INDF register takes place at the memory location pointed at by FSR. For example, if the FSR register is initialized to memory address 0x20, then clearing the INDF register has the effect of clearing the memory location at address 0x20. In other words, the action on the INDF register actually takes place at the address contained in the FSR register. Now, if FSR (the pointer register) is incremented and INDF is again cleared, the memory location at address 0x21 is cleared. Indirect addressing is covered in detail in the programming chapters.

8.5 Mid-range I/O and Peripheral Modules

Mid-range devices contain special modules to implement peripheral and I/O functions. The more complex the device the more peripheral modules are likely to be present. For example, a simple mid-range PIC like the 16F84A contains few peripheral modules, specifically, EEPROM data memory, I/O ports, and a timer module. The 16F87x PICs, on the other hand, in addition to I/O ports, EEPROM, and three individual timers, have a parallel slave port, a WPM (capture and compare) module, an MSSP (master synchronous serial port) module, a USART (universal asynchronous/synchronous receiver and transmitter) module, and an A/D (analog-to-digital converter) module.

Other members of the mid-range family have additional or different peripheral and I/O modules. In the following sections, we briefly describe the architecture of the most common peripheral modules. The programming details are covered elsewhere in the book.

Implementation of many different functions in a device with a small footprint requires multiplexing many of the PIC’s access connections. Figure 8-10 shows the pinout of the 16F84A and the 16F877 and the multiple functions of most pins in both devices.

Figure 8-10 16F84A and 16F877 Pin Diagrams

8.5.1 I/O Ports

Ports provide PICs access to the outside world and are mapped to physical pins on the device. In some mid-range PICs (see Figure 8-10) some port pins for I/O ports are multiplexed with alternate functions of peripheral modules. When a peripheral module is enabled, that pin ceases to be a general purpose I/O.

Port pins can be configured either as input or output, that is, general ports are bidirectional. Each port has a corresponding TRIS register which determines if a port is designated as input or output. A value of 1 in the port’s TRIS register makes the port an input and a value of 0 makes the mapped port an output. Typically, input ports are used in communicating with input devices, such as switches, keypads, and input data lines from hardware devices. Output ports are used in communicating with output devices, such as LEDs, seven-segment displays, LCDs (liquid-crystal displays), and data output lines to hardware devices.

Although port pins are bitmapped, they are read and written as a unit. For example, the PORTA register holds the status of the eight pins possibly mapped to Port-A, while writing to PORTA writes to the port latches. Write operations to ports are actually read-modify-write operations. In other words, the port pins are first read, then the value is modified, and then written to the port’s data latch. Some of the port pins are multiplexed; for example, pin RA4 is multiplexed with the Timer0 module clock input; therefore, it is labeled RA4/T0CKI pin. Other PORTA pins are multiplexed with analog inputs and with other peripheral functions. The device data sheets contain information about the functions assigned to each device pin.

8.5.2 Timer Modules

Timer modules are available in all mid-range devices. The TIMER0 module is present in all PICs of this family. It has the following features:

1.8-bit timer/counter

2.Readable and writable

3.8-bit software programmable prescaler

4.Internal or external clock select

5.Interrupt on overflow from FFh to 00h

6.Edge select for external clock

Chapter 12 is devoted entirely to the architecture and programming of timers and counters.

8.5.3 Capture-and-Compare Module

Some mid-range devices contain one or more capture-and-compare modules, designated as Capture/Compare/PWM modules. In Figure 8-10 you can see that one of the functions multiplexed onto pin 17 of the 16F877 is labeled CCP1 (cap- ture-and-compare module number 1). The CCP2 module is multiplexed onto pin number 16. The principal function of the capture-and-compare modules is to enhance timer operations. Each module contains the following elements:

• A 16-bit register which can operate as:

a16-bit capture register or a 16-bit compare register

•A PWM Master/Slave Duty Cycle register

When more than one capture-and-compare module is implemented in a single device, they are all identical in operation. In the 16F877, the two available modules are designated as CCP1 and CCP2 respectively. In each module a Capture/Compare/PWM Register1 (CCPR1) is comprised of two 8-bit registers: CCPR1L (low byte) and CCPR1H (high byte). The CCP1CON register controls the operation of CCP1.

The CCP modules find use in recording events, measuring time periods, counting, generating pulses and periodic waveforms, and voltage averaging, among others. However, since these applications are not commonly found in the simple PIC circuits covered in this book we make no further reference to this topic.

8.5.4 Master Synchronous Serial Port (MSSP) Module

Some mid-range PICs come equipped with hardware modules to implement serial protocols, including SPI and I2C. The module that provides these interfaces is named the Master Synchronous Serial Port, or MSSP. The MSSP module can operate in either the slave or the master mode, as well as in a free-bus mode, also called the multi-master function.

The MSSP module is useful for communicating with other peripheral or microcontroller devices. The peripheral devices can be serial EEPROMs, shift registers, display drivers, A/D converters, etc. The MSSP module is discussed in Chapter 8, in the context of EEPROM data memory programming.

8.5.5 USART Module

The Universal Synchronous Asynchronous Receiver Transmitter (USART) module in the 16F87x family is also known as a Serial Communications Interface, or SCI. The USART module is used in communicating with devices and systems that support RS-232 communications, including computers and terminals. It can be configured as an asynchronous full duplex device, as a synchronous half-duplex master, or as a synchronous half-duplex slave. In the synchronous mode, the USART is useful in communicating with analog-to-digital and digital-to-analog integrated circuits or for accessing serial EEPROMS. The USART is discussed extensively in Chapter 14 and, in the context of programming serial EEPROMS, in Chapter 15.

8.5.6 A/D Module

Until recently, A/D conversions required the use of dedicated devices, usually in the form of an integrated circuit component. Mid-range PICs now come with on-board A/D hardware. One of the advantages of using on-board A/D converters is saving interface lines. Interfacing with a hardware IC usually requires three to four lines. A similar function can be implemented with on-board A/C hardware with a single line. Since I/O lines are often needed in PIC circuits, the advantage of on board A/C hardware is significant.

Mid-range PICs equipped with A/D converters have either 8- or 10-bit resolution and can receive analog input in 2 to 16 different channels. For example, the 16F877 contains eight analog input channels at a 10-bit resolution. An A/D converter uses a sample-and-hold capacitor to store the analog charge and performs a successive approximation algorithm to produce the digital result. When the converter resolution is 10 bits these are stored in two 8-bit registers, one of them having only four significant bits.

The A/D module has highand low-voltage reference inputs which are selected by software. The module can operate while the processor is in the SLEEP mode, but only if the A/D clock pulse is derived from its internal RC oscillator. The A/D converter module is discussed in detail in Chapter 16.