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Note that the opcode field has variable number of bits in the PIC instruction set. This scheme allows implementing 35 different instructions while using a minimum of the 14 available opcode bits. Also note that instructions that reference a file register do so in a 7-bit field. The numerical range of seven bits is 128 values. For this reason, the mid-range PICs that address more than 128 data memory locations must resort to banking techniques. In this case, a bit or bit field in the STATUS register serves to select the bank currently addressed.
A similar situation arises when addressing program memory with an 11-bit field. Eleven bits allow 2048 addresses, so if a PIC is to have more than 2K program memory it is necessary to adopt a paging scheme in which a special function register is used to select the memory page where the instruction is located. Paging is required only in devices that exceed the 2K program space limit that can be encoded in 11 bits.
8.0.5 Mid-Range Device Versions
The device names used by Microchip use different encodings to represent different versions of the various devices. For example, the first letter following the family affiliation designator represents the memory type of the device, as follows:
1.The letter C, as in PIC16Cxxx, refers to devices with EPROM type memory.
2.The letters CR, as in PIC16CRxxx, refer to devices with ROM type memory.
3.The letter F, as in PIC16Fxxx, refers to devices with flash memory.
The letter L immediately following the affiliation designator refers to devices with an extended voltage range. For example, the PIC16LFxxx designation corresponds to devices with extended voltage range.
8.1 The Mid-range Core Features
Core features refer to the device oscillator, reset mechanism, CPU architecture and operation, Arithmetic-Logic Unit, memory organization, interrupts, and instruction set. We have already referred to the architecture and general features of the CPU. Memory organization is discussed in a separate section later in this chapter. The remaining topics are covered in the following subsections.
8.1.1 Oscillator
Mid-range PICs require an external device to produce the clock cycles required for its operation. The PIC executes an instruction every four clock cycles, so the oscillator speed determines the device performance.
Mid-range PICs support up to eight different oscillator modes. For example, in the 16F877, any of the eight modes can be used, while in the 16F84 only four oscillator modes are available. The oscillator mode is selected at device programming time and cannot be changed at runtime. The configuration bits, which are non-volatile flags set during device programming, determine which oscillator mode is used by the program, among the following:
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1.LP Low Frequency Crystal
2.XT Crystal Resonator
3.HS High Speed Crystal Resonator
4.RC External Resistor/Capacitor
5.EXTRC External Resistor/Capacitor
6.EXTRC External Resistor/Capacitor with CLKOUT
7.INTRC Internal 4 MHz Resistor/Capacitor
8.INTRC Internal 4 MHz Resistor/Capacitor with CLKOUT
The resistor/capacitor oscillator option is the least expensive to implement, but also the least accurate one. This option is used only in systems where clock accuracy and consistency are not issues. The low-power frequency crystal option is the one with lowest power consumption and can be used in systems where the power consumption element is important.
The first three oscillator modes (LP, XT, and HS) allow selecting different frequency ranges. The HS option has the highest frequency range and consumes the most power. The XT option is based on a standard crystal resonator and has a mid-range power consumption. The LP option has low gain and consumes the least power of the three crystal modes. The general rule is to use the oscillator with the lowest possible gain that still meets the circuit requirements. The RC mode with EXTRC and CLKOUT features has the same functionality as the straight RC oscillator option.
The XT option (crystal resonator) can be purchased in a ceramic package. This device, called a ceramic resonator, contains three pins. The ones on the extremes are connected to the corresponding oscillator input lines on the PIC, labeled OSC1 and OSC2. The center pin is connected to ground. Figure 8-3 shows the circuit diagram for an oscillator and a crystal resonator.
C1
OSC
XTAL
C2
Figure 8-3 Circuit Diagram for Oscillators
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Alternatively, the oscillator function is provided by an integrated circuit (such as the ICS502) that can generate several different clock frequencies. Some circuits, especially in PIC demonstration boards, contain jumper pins that allow selecting among several clock rates.
8.1.2 System Reset
The reset mechanism places the PIC in a known condition. The reset mechanism is used to gain control of a runaway or hung-up program, as a forced interrupt in program execution, or to make the device ready at program load time. The processor’s !MCLR pin produces the reset action when it reads logic zero. The exclamation sign preceding the pin’s name (or a line over it) indicates that the action is active-low. To prevent accidental resets the !MCLR pin must be connected to the positive voltage supply through a 5K or 10K resistor. When a resistor serves to place a logic one on a line it is called a pull-up resistor.
The mid-range PICs are capable of several reset actions:
1.Reset during power on (POR).
2.!MCLR reset during normal operation.
3.Reset during SLEEP mode.
4.Watchdog timer reset (WDT).
5.Brown-out reset (BOR).
6.Parity error reset.
The first two reset sources in the preceding list are the most common. POR reset serves to bring all PIC registers to an initial state, including the program counter register. The second source of reset action takes place when the !MCLR line is intentionally brought down, usually by the action of a push-button reset switch. This switch is useful during program development since it provides a way of forcefully restarting execution. Figure 8-4 shows a typical wiring of the !MCLR line to provide a reset action.
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RA3 |
RA0 |
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RA4/TOCKI |
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!MCLR |
OSC2 |
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Vss |
Vdd |
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RB0/INT |
RB7 |
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RB1 |
RB6 |
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RB5 |
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Figure 8-4 Typical Wiring of the Reset Switch
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The second one is a product of purposefully bringing-in a logical zero to the MCLR pin during normal operation of the microcontroller. This second one is often used in program development.
User RAM memory is not affected by a reset. The GPRs (general purpose register) are in an unknown state during power-up and are not changed by reset. SFR registers, on the other hand, are reset to an initial state. The initialization conditions for each of the SFRs are found in the device data sheet. The most important of these is the program count (PC) which is reset to zero. This action directs execution to the first instruction and effectively restarts the program.
During power-up the processor itself initiates a reset and the power supply voltage increases from 1.2 to 1.8V. Several bits in various registers are related to the reset action, but these are not available in all mid-range devices. For example, some high-end devices in the mid-range group, such as the 16F87x, contain two re- set-related bits in the PCON register. One of them (named !POR) determines the power-on reset status. The other one (named !BOR) informs about the brown-out reset status. However, the PCON register does not exist in the 16F84 or 16F84A.
8.1.3 Interrupts
The interrupt mechanism provides a way of having the microcontroller respond to events as they occur, rather than having to poll devices in order to determine their state. Thus, the interrupt works like a “tap on the shoulder” on the microcontroller, calling its attention to an event that requires an action or device that needs servicing. After responding to or ignoring the interrupt, the CPU resumes processing where it left off.
In computer technologies the interrupt mechanism is a complicated hardware/software system that often includes programmable interrupt controller ICs. Processors and microprocessors usually support hardware and software interrupts and maskable and non-maskable interrupts; interrupts originate in practically any device connected to the system. In the PICs, the interrupt mechanism is much simpler and varies considerably even among members of the same PIC family.
All PICs of the mid-range family to some degree support interrupts. The interrupt source usually originates in one of the hardware modules, although some sources generate more than one interrupt. The following are interrupt sources in the mid-range family, although not all are supported by every PIC.
•INT Pin Interrupt (external interrupt)
•TMR0 Overflow Interrupt
•PORTB Change Interrupt
•Comparator Change Interrupt
•Parallel Slave Port Interrupt
•USART Interrupts
•Receive and Transmit Interrupt