The selection depends on the specific microcontroller, the circuit requirements, and the cost of each available option. The least expensive option is the resistor/capacitor oscillator circuit (RC network). The disadvantages are its slow speed and inherent inaccuracies. Some of the newer generations of microcontrollers come equipped with an internal RC oscillator that operate as a programmable timer. Typical speeds are 4 MHz with a 1.5 percent error. The actual use and implementation of microcontroller clocks is discussed in relation to each specific device.

6.3 Frequency Dividers and Counters

Frequency dividers and counters are actually the same circuitry used in different ways. Counters are one of the most useful and versatile digital devices. Counters can be used to count the number of clock cycles and as an instrument for measuring time and therefore period or frequency. The two different types of counters are synchronous and asynchronous.

6.3.1 Frequency Dividers

Circuit designers often needed to reduce the frequency of a wave clock signal. One easy way of doing it is to divide the frequency by two, which is done by feeding back the not-Q output of a D-type flip-flop to its data line. Figure 6-14 shows a divide-by-2 circuit and its effect on the resulting wave.

Figure 6-14 A Divide-by-two Circuit

In the circuit of Figure 6-14 the frequency division occurs because each input clock rising edge toggles the flip-flop’s output. When the Q output goes low, the not-Q line goes high and the high feedback signal is fed back to the data line, thus canceling out the next high wave of the f signal.

6.3.2 The JK Flip-flop Counter

One type of specialized flip-flop that we did not cover in Section 6.2 is the JK flip-flop. The JK flip-flop is an ideal component to build a circuit that keeps track of the number of positive or negative clock edges on the input clock. The name of this flip-flop relates to the two variables, J and K, that are used as inputs to the circuit. Figure 6-15 shows one possible circuit implementation for the JK flip-flop.

6.3.4 Decoding Gates

A decoding gate is a way of connecting the output of a counter so that it signals a given state. For example, if four D-type flip-flops are wired so as to produce a four-bit ripple counter similar to the one in Figure 6-15, the counter represents binary digits 0000 to 1111. If we wanted to detect the value 1101 (16 decimal) the resulting circuit could be designed as in Figure 6-17.

1101

Figure 6-17 Decoding Gate

The circuit of Figure 6-17 uses a NOR gate to invert the value of bit number 1. Then the AND gate serves to trigger the output when bits 0, 2, and 3 are high and bit 1 is low. This corresponds to the binary value 1011.

6.3.5 Synchronous Counters

Although the ripple counter is the simplest one, it has the previously mentioned disadvantage that each flip-flop has to wait for its neighbor to switch states. This means that in a ripple counter the delay times are additive, and also that the total “settling” time for the counter is approximately the delay multiplied by the total number of flip-flops. In addition, with ripple counters the resulting delay creates the possibility of glitches occurring at the output of decoding gates. These problems can be overcome by the use of a synchronous or parallel counter.

By observing how counting takes place in binary numbers, a counter in which each flip-flop is triggered at every clock beat can be built. Binary counting has the property that when a bit changes from high to low (1 to 0) it sends a toggle command to its neighbor to the left. So assuming that the low-order bit changes consecutively from one state to its complement, and starting from all bits initialized to 0, binary counting can be visualized as in Figure 6-18.

In Figure 6-19 note that the first flip-flop (the one with the Q0 output) has a posi- tive-edge triggered clock input. The lowest-order flip-flop toggles with each rising edge of the clock signal (not shown in the illustration). The second flip-flop to the right toggles with every falling edge of the signal from its neighbor to the left. And so on to the last flip-flop in the chain. The arrows in the waveform portion of Figure

6-19 show that each succeeding output bit is toggled by the transition from high to low of its lower-ordered neighbor. Also note the dashed line that marks the point where all found counters are transitioning from high-to-low. At this point all four counters wrap around to zero and a new count begins.

Observe that the not-Q output line transitions opposite to the Q output. That is, when the Q output line goes high, not-Q goes low, and viceversa. So if the pulse into each successive flip-flop originated in the not-Q line, instead of the Q line, then the resulting circuit would be a synchronous counter that transitions on the positive edge (low-to-high) instead of in the negative edge, as is the case with the counter in

Figure 6-19. Furthermore, the not-Q line provides a set of negated outputs in reference to the Q lines; therefore, it is possible to come up with a circuit that serves both as an upand down-counter according to the selected set of outputs. Such a circuit is shown in Figure 6-20.

+5V

wave input

Figure 6-20 Synchronous 4-bit Upand Down-counter

In the counter of Figure 6-20 the Q outputs generate the up-count series while the not-Q outputs produce the down-count series.

6.3.6 Counter ICs

Counters are available as standard TTL components. The 7493 is an asynchronous 4-bit ripple counter that counts from 0 to 15. The 7490 is another version of the ripple counter, called a decade counter, since the count output is in the range 0 to 9. The 74193 is a 4-bit synchronous up/down counter in the range 0 to 15. Figure 6-21 is a pin diagram of the 74193.

Figure 6-21 74193 Asynchronous Up/Down Counter Pin Diagram

The 74193 is a synchronous counter, so its output changes precisely at each clock pulse. This is convenient since it allows connecting its output to other logic gates and avoids the glitches associated with ripple counters. Note from Figure 6-21 that the 74194 has separate clock inputs for counting up and counting down. The count increases as the up clock input becomes high (on the rising-edge). The count decreases as the down clock input becomes high (on the rising-edge). In both cases the other clock input should be high. For normal operation the Preset input should be high and the Reset input low. When the Reset input is high it resets the count to zero, that is, lines QA to QD are low. The counter can be preset by placing any desired binary number on inputs A to D and making the Preset input low. These inputs may be left unconnected if not required.

Several 74193 counters can be chained by wiring a common Reset line, connecting the carry to the up clock line of the next counter and the borrow to the down line.

6.3.7 Shift Registers

In chapter 4 we discussed logical operations that shift and rotate the operand bits. These manipulations are useful in inspecting individual bits, in performing fast multiplications, in implementing time delays, and in converting parallel input to serial output, and vice versa. The hardware implementation of shift-and-rotate operations are called shift counters or shift registers.

Shift counters are often based on the D-type flip-flop. Actually, several D-type flip-flops can be chained together so that the D output of one goes into the D input of the next one. If all the flip-flops are driven by the same clock signal, then the effect would be to shift the bits from one flip-flop into the next one at each rising clock pulse.

A common implementation of a shift counter is called a parallel-in/serial-out shift register, as the one in Figure 6-22.

load

CLOCK

Figure 6-22 Four-Bit Parallel-In/Serial-Out Shift Counter

The circuit in Figure 6-22 shows four flip-flops connected so that the output of one feeds into the input of the next one. Also, a set of NAND gates allow parallel data input. When the load signal is set high the flip-flops in the shift register are loaded simultaneously with the logic values at the inputs A, B, C, and D. The 74165 IC is an 8-bit parallel-in/serial-out shift register with asynchronous parallel load and two OR-gated clock inputs. Figure 6-23 is a pin diagram of the 74165 IC.

Figure 6-23 Pin Diagram of IC 74165

The serial input line in the diagram of Figure 6-22 and in the 74165 IC in Figure 6-23 allows cascading multiple chips.

Parallel-in/serial-out shift registers find common use in the implementation of serial ports. In serial communications data is sent one bit at a time over a single wire.