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Universal Serial Bus Specification Revision 2.0

Host

 

 

Hub

FS/LS

 

 

(SS: start sp. status

device

(data toggle)

 

 

 

 

CS: comp. sp. status)

 

 

 

(data toggle)

0

 

 

SS:Free/x

0

uFrame M

st1

SSPLIT

st1

 

 

 

 

 

 

st2

OUT

st2

 

 

 

 

 

 

sd1

DATA0

sh1

 

 

 

 

 

 

 

 

SS:Pending/x

 

uFrame M+1

 

 

 

 

OUT

DATA0

1

ACK

uFrame M+2

ct1

CSPLIT

ct1

CS:Ready/ack

 

 

 

 

ct2

OUT

ct2

 

 

 

 

 

 

 

NYET

ch5

 

 

TRANS_ERR

 

 

 

ce1->ce6

 

 

 

 

ct1

CSPLIT(retry imm.)

 

 

 

ct1

 

 

 

 

 

 

ct2

OUT

ct2

 

 

 

 

 

 

ch6

NYET

ch5

 

 

 

 

 

uFrame M+3

ct1

CSPLIT

 

 

 

 

ct1

 

 

 

 

 

 

ct2

OUT

ct2

 

 

 

 

 

 

 

ACK

ch2

CS:Old/ack

 

ch2

 

 

 

 

 

1

 

 

 

 

uFrame M+4 Host does not issue 3rd CSPLIT,

SS:Free/x

 

because host already receives ACK

CS:Free/x

 

on previous microframe.

 

 

uFrame M+5

Figure A-58. CS Earlier HS NYET Smash

503

Universal Serial Bus Specification Revision 2.0

Host

 

 

Hub

FS/LS

 

 

(SS: start sp. status

device

(data toggle)

 

 

 

 

CS: comp. sp. status)

 

 

 

(data toggle)

0

 

 

SS:Free/x

0

uFrame M

st1

SSPLIT

st1

 

 

 

 

 

 

st2

OUT

st2

 

 

 

 

 

 

sd1

DATA0

sh1

 

 

 

 

 

 

 

 

SS:Pending/x

 

uFrame M+1

 

 

 

 

OUT

DATA0

1

ACK

uFrame M+2

ct1

CSPLIT

ct1

CS:Ready/ack

 

 

 

 

ct2

OUT

ct2

 

 

 

 

 

 

 

NYET

ch5

 

 

TRANS_ERR

 

 

 

ce1->ce6

 

 

 

 

ct1

CSPLIT

ct1

 

 

 

 

 

 

ct2

OUT

ct2

 

 

 

 

 

 

 

NYET

ch5

 

 

TRANS_ERR

 

 

 

ce1->ce6

 

 

 

 

ct1

CSPLIT

ct1

 

 

 

 

 

 

ct2

OUT

ct2

 

 

 

 

 

 

 

NYET

ch5

 

 

TRANS_ERR

 

 

 

ce1->ce5

 

 

 

 

ENDPOINT HALT

 

 

uFrame M+3 Host does not issue 2nd CSPLIT,

CS:Free/x

 

because this endpoint is already

 

 

ENDPOINT HALT.

 

 

uFrame M+4 Host does not issue 3rd CSPLIT,

SS:Free/x

 

because this endpoint is already

 

 

ENDPOINT HALT.

 

 

Figure A-59. CS Earlier HS NYET 3 Strikes Smash

504

Universal Serial Bus Specification Revision 2.0

Host

(data toggle)

0

 

 

 

uFrame M

st1

SSPLIT

st1

 

 

 

 

st2

OUT

st2

 

 

 

 

sd1

DATA0

sh1

 

 

 

uFrame M+1

 

 

 

uFrame M+2

ct1

CSPLIT

ct1

 

 

 

 

ct2

OUT

ct2

 

 

 

 

ch6

NYET

ch5

 

 

 

uFrame M+3

ct1

CSPLIT

 

 

ct1

 

 

 

 

ct2

OUT

ct2

 

 

 

 

ch6

NYET

ch5

 

 

 

uFrame M+4

ct1

CSPLIT

 

 

ct1

 

 

 

 

ct2

OUT

ct2

 

 

 

 

ce7

NYET

ch5

 

 

 

 

ce3

 

 

uFrame M+8

 

SSPLIT(retry)

 

st1

 

 

st1

 

 

 

 

st2

OUT

st2

 

 

 

 

sd1

DATA0

sh1

 

 

 

Hub

(SS: start sp. status CS: comp. sp. status)

SS:Free/x

SS:Pending/x

OUT

DATA0

SS:Free/x

Hub stops sending this data and forces a bit stuffing error.

SS:Pending/x

FS/LS device

(data toggle) 0

uFrame M+9

OUT

DATA0

1

ACK

 

 

 

CS:Ready/ack

uFrame M+10

ct1

CSPLIT

ct1

 

 

 

 

ct2

OUT

ct2

 

 

 

 

 

ACK

CS:Old/ack

 

ch2

ch2

 

 

 

1

 

 

 

Figure A-60. Abort and Free Abort(FS/LS Transaction is Continued at End of M+3)

505

Universal Serial Bus Specification Revision 2.0

Host

(data toggle) 0

uFrame M

st1

st2

sd1

uFrame M+1

 

uFrame M+2

ct1

 

ct2

 

ch6

uFrame M+3

ct1

 

 

ct2

 

ch6

uFrame M+4

ct1

 

 

ct2

 

ce7

 

ce3

uFrame M+8

 

 

st1

 

st2

 

sd1

Hub

(SS: start sp. status CS: comp. sp. status)

SS:Free/x

SSPLIT st1

OUT st2

DATA0 sh1

SS:Pending/x

CSPLIT

ct1

OUT

ct2

NYET ch5

CSPLIT

ct1

OUT

ct2

NYET ch5

SS:Free/x

Hub frees this transaction from SS.

CSPLIT

ct1

OUT

ct2

NYET ch5

FS/LS device

(data toggle) 0

SSPLIT(retry)

st1

OUT

st2

DATA0

sh1

SS:Pending/x

uFrame M+9

OUT

DATA0

1

ACK

 

 

 

CS:Ready/ack

uFrame M+10

ct1

CSPLIT

ct1

 

 

 

 

ct2

OUT

ct2

 

 

 

 

 

ACK

CS:Old/ack

 

ch2

ch2

 

 

 

1

 

 

 

Figure A-61. Abort and Free Free(FS/LS Transaction is not Started at End of M+3)

506

Universal Serial Bus Specification Revision 2.0

Host

 

 

Hub

 

 

(SS: start sp. status

(data toggle)

 

 

 

 

CS: comp. sp. status)

 

 

 

0

 

 

SS:Free/x

uFrame M

st1

SSPLIT

st1

 

 

 

 

st2

OUT

st2

 

 

 

 

sd1

DATA0

sh1

 

 

 

 

 

 

SS:Pending/x

uFrame M+1

 

 

 

 

 

 

 

CS:Ready/nak

uFrame M+2

ct1

CSPLIT

ct1

 

 

 

 

 

 

ct2

OUT

ct2

 

 

 

 

 

 

 

NAK

ch3

CS:Old/nak

 

ch3

 

 

 

 

 

uFrame M+3 Host does not issue 2nd CSPLIT,

CS:Free/x

 

because host already receives NAK

 

 

on previous microframe.

 

 

uFrame M+4 Host does not issue 3rd CSPLIT,

SS:Free/x

 

because host already receives NAK

 

 

on previous microframe.

 

 

uFrame M+8

 

SSPLIT(retry)

 

 

st1

 

 

 

st1

 

 

 

 

 

 

st2

OUT

st2

 

 

 

 

 

 

sd1

DATA0

 

 

sh1

SS:Pending/x

uFrame M+9

 

 

 

CS:Ready/ack

uFrame M+10

ct1

CSPLIT

ct1

 

 

 

 

ct2

OUT

ct2

 

 

 

 

 

ACK

CS:Old/ack

 

ch2

ch2

 

 

 

1

 

 

 

FS/LS device

(data toggle) 0

OUT

DATA0

NAK

OUT

DATA0

1

ACK

Figure A-62. Device Busy No Smash(FS/LS NAK)

507

Universal Serial Bus Specification Revision 2.0

Host

(data toggle)

 

0

 

 

uFrame M

st1

SSPLIT

st1

 

 

 

 

st2

OUT

st2

 

 

 

 

sd1

DATA0

sh1

 

 

 

Hub

(SS: start sp. status CS: comp. sp. status)

SS:Free/x

SS:Pending/x

FS/LS device

(data toggle) 0

uFrame M+1

OUT

DATA0

1

STALL

CS:Ready/stall

uFrame M+2

ct1

CSPLIT

ct1

 

 

 

 

ct2

OUT

ct2

 

 

 

 

ch1

STALL

ch1

 

 

 

 

ENDPOINT HALT

 

 

uFrame M+3 Host does not issue 2nd CSPLIT,

CS:Free/x

because this endpoint is already

 

ENDPOINT HALT.

 

 

uFrame M+4 Host does not issue 3rd CSPLIT,

SS:Free/x

because this endpoint is already

 

ENDPOINT HALT.

 

 

Figure A-63. Device Stall No Smash(FS/LS STALL)

508

Universal Serial Bus Specification Revision 2.0

A.4 Interrupt IN Transaction Examples

Legend:

(S): Start Split

(C): Complete Split

Summary of cases for Interrupt OUT transaction

Normal cases

Case

No smash

(FS/LS data packet is on M+1)

HS SSPLIT smash

HS SSPLIT 3 strikes smash

HS IN(S) smash

HS IN(S) 3 strikes smash

HS CSPLIT smash

HS CSPLIT 3 strikes smash

HS IN(C) smash

HS IN(C) 3 strikes smash

HS DATA0/1 smash

HS DATA0/1 3 strikes smash

FS/LS IN smash

FS/LS IN 3 strikes smash

FS/LS DATA0/1 smash

FS/LS DATA0/1 3 strikes smash

FS/LS ACK smash

FS/LS ACK 3 strikes smash

Reference

Figure

Figure A-64

Figure A-65

No figure

No figure

Figure A-66

Figure A-67

Figure A-68

Figure A-69

Figure A-70

No figure

Figure A-71

No figure

Figure A-72

No figure

Similar Figure

Figure A-65

Figure A-66

Figure A-67

509

Universal Serial Bus Specification Revision 2.0

Searcing

 

 

 

 

 

 

 

Case

Reference

Similar Figure

 

 

Figure

 

 

 

 

 

 

No smash

Figure A-73

 

 

 

 

 

CS(Complete-split transaction) earlier cases

Case

Reference

Similar Figure

 

Figure

 

 

 

 

No smash (HS MDATA and FS/LS transaction is on M+1 and M+2)

No smash (HS NYET and FS/LS transaction is on M+2)

No smash (HS NYET and MDATA and FS/LS transaction is on M+2 and M+3)

No smash (HS NYET and FS/LS transaction is on M+3)

HS NYET smash

HS NYET 3 strikes smash

Figure A-74

Figure A-75

Figure A-76

Figure A-77

Figure A-78

Figure A-79

Abort and Free cases

Case

Reference

Similar Figure

 

Figure

 

 

 

 

No smash and abort (HS NYETand FS/LS transaction is continued at end of M+3)

No smash and free(HS NYETand FS/LS transaction is not started at end of M+3)

Figure A-80

Figure A-81

FS/LS transaction error cases

Case

Reference

Similar Figure

 

Figure

 

 

 

 

HS ERR smash

 

Figure A-68

 

 

 

HS ERR 3 strikes smash

 

Figure A-69

 

 

 

510

Universal Serial Bus Specification Revision 2.0

Device busy cases

 

 

 

 

 

 

 

Case

Reference

Similar Figure

 

 

Figure

 

 

 

 

 

 

No smash(HS NAK(C))

Figure A-82

 

 

 

 

 

 

HS NAK(C) smash

 

Figure A-68

 

 

 

 

 

HS NAK(C) 3 strikes smash

 

Figure A-69

 

 

 

 

 

FS/LS NAK smash

 

Figure A-71

 

 

 

 

 

FS/LS NAK 3 strikes smash

No figure

 

 

 

 

 

Device stall cases

Case

Reference

Similar Figure

 

Figure

 

 

 

 

No smash

HS STALL(C) smash

HS STALL(C) 3 strikes smash

FS/LS STALL smash

FS/LS STALL 3 strikes smash

Figure A-83

No figure

Figure A-68

Figure A-69

Figure A-71

511

Universal Serial Bus Specification Revision 2.0

Host

 

 

Hub

 

 

(SS: start sp. status

(data toggle)

 

 

 

 

CS: comp. sp. status)

 

 

 

0

 

 

SS:Free/x

uFrame M

st1

SSPLIT

st1

 

 

 

 

st2

IN

st2

 

 

 

 

 

 

SS:Pending/x

uFrame M+1

 

 

 

 

 

 

 

CS:Ready/lastdata

uFrame M+2

ct1

CSPLIT

ct1

 

 

 

 

 

 

ct2

IN

ct2

 

 

 

 

 

 

ch7

DATA0

cd1

CS:Old/lastdata

 

 

 

 

1

 

 

 

 

uFrame M+3 Host does not issue 2nd CSPLIT,

CS:Free/x

 

because host already receives

 

 

DATA0 on previous microframe.

 

FS/LS device

(data toggle) 0

IN

DATA0

ACK

1

uFrame M+4 Host does not issue 3rd CSPLIT,

SS:Free/x

because host already receives

 

DATA0 on previous microframe.

 

uFrame M+5

Figure A-64. Normal No Smash(FS/LS Data Packet is on M+1)

512

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