10.6.6External Memory Read – Overlays & I/O Memory

Memory Interface 10

external signals: PMS, DMS, IOMS, BMS, CMS, RD, and WRremain high (deasserted), and the address and data buses are tristated.

10.6.7External Memory Write – Overlays & I/O Memory

External memory writes may access either PM overlays, DM overlays, or I/O memory space. These read operations occur in the following sequence (see Figure 10.35):

1)The ADSP-2181 executes a write to an external memory address; the address is driven on the address bus, data is driven on the data bus, and PMS, DMS,

BMS, or IOMS, and WRis asserted. ( CMSmay also be asserted, depending how it is configured.)

2)The external peripheral stores the data.

3)The ADSP-2181 stops driving the address and data buses and deasserts WR.

CLKOUT

A0 – A13

DMS, PMS, BMS, IOMS, or CMS

WR

DATA

Figure 10.35 External Memory Write Timing

RDremains high (deasserted) throughout the external memory write operation.

10.7MEMORY INTERFACE SUMMARY (ALL PROCESSORS)

Table 10.5 summarizes the states of the memory interface pins for various combinations of program memory and data memory accesses. Table 10.6

summarizes the states of the memory interface and control pins during 10 – 37 reset, booting (ADSP-21xx boot memory booting, not ADSP-2181 byte

memory booting), and bus grant.