Register set
User |
FIQ |
IRQ |
SVC |
Undef |
Abort |
r0
r1
r2
r3
r4
r5
r6
r7
r8
r9
r10
r11
r12
r13 (sp)
r14 (lr)
r15 (pc)
cpsr
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r15, |
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User |
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cpsr |
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r0 |
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r12, |
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r0 |
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r12, |
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r0 |
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r12, |
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r0 |
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r12, |
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r15, |
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r15, |
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r15, |
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r15, |
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r8 |
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cpsr |
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cpsr |
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cpsr |
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r9 |
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r10 |
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r11 |
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r12 |
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r13 (sp) |
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r13 (sp) |
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r13 (sp) |
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r13 (sp) |
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r14 (lr) |
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r14 (lr) |
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r14 (lr) |
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r14 (lr) |
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r14 (lr) |
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spsr |
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spsr |
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spsr |
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spsr |
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spsr |
Thumb state Low registers
Thumb state High registers
Program Status Registers
31 |
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28 27 24 |
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23 |
16 |
15 |
8 |
7I 6 F5 T4 |
0 |
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N Z |
C |
V |
Q |
J |
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U n d e f |
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i n e d |
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c |
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f |
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s |
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x |
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•Condition code flags
–N = Negative result from ALU
–Z = Zero result from ALU
–C = ALU operation Carried out
–V = ALU operation oVerflowed
•Sticky Overflow flag - Q flag
–Architecture 5TE/J only
–Indicates if saturation has occurred
•J bit
–Architecture 5TEJ only
–J = 1: Processor in Jazelle state
•Interrupt Disable bits.
–I = 1: Disables the IRQ.
–F = 1: Disables the FIQ.
•T Bit
–Architecture xT only
–T = 0: Processor in ARM state
–T = 1: Processor in Thumb state
•Mode bits
–Specify the processor mode
Various OS support
Linux
•Chrome OS
•Debian
•Fedora
•Gentoo
•iPodLinux
•Maemo
•MeeGo
•Ubuntu
Other:
ReactOS, Symbian OS, Windows 8
BSD
•FreeBSD
•NetBSD
•OpenBSD
•iOS
Solaris
•OpenSolaris
Preview of the next version
27 October 2011 new ARMv8-architecture was released:
•64-bit instruction set
•2 execution states: AArch32 and AArch64.
–V8 will support all 32-bit existing instructions and introduce a new 64-bit instruction set.
•Support all existing features:
–TrustZone
–Virtualization
–NEON
–…
* expected till 2014
Licensees
