- •Features
- •Logic block diagram
- •Pin arrangement
- •Selection guide
- •Functional description
- •Absolute maximum ratings
- •Truth table
- •Recommended operating conditions
- •DC operating characteristics (over the operating range)1
- •Capacitance (f = 1MHz, Ta = room temperature, VCC = NOMINAL)2
- •Read cycle (over the operating range)3,9
- •Key to switching waveforms
- •Read waveform 1 (address controlled)3,6,7,9
- •Read waveform 2 (CE controlled)3,6,8,9
- •Write cycle (over the operating range)11
- •Write waveform 1 (WE controlled)10,11
- •Write waveform 2 (CE controlled)10,11
- •Data retention characteristics (over the operating range)13
- •Data retention waveform
- •AC test conditions
- •Notes
- •2 This parameter is sampled, but not 100% tested.
- •5 This parameter is guaranteed, but not tested.
- •6 WE is High for read cycle.
- •7 CE and OE are Low for read cycle.
- •8 Address valid prior to or coincident with CE transition Low.
- •12 CE1 and CE2 have identical timing.
- •13 2V data retention applies to the commercial operating range only.
- •14 C=30pF, except on High Z and Low Z parameters, where C=5pF.
- •Typical DC and AC characteristics
- •Package diagrams
- •Ordering information
- •Part numbering system
January 2001 |
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AS7C256 |
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Advance Information |
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AS7C3256 |
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5V/3.3V 32K X 8 CMOS SRAM (Common I/O) |
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Features |
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• AS7C256 (5V version) |
- 7.2 mW (AS7C3256) / max CMOS I/O |
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• AS7C3256 (3.3V version) |
• 2.0V data retention |
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• Industrial and commercial temperature |
• Easy memory expansion with |
CE |
and |
OE |
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• Organization: 262,144 words × 16 bits |
• TTL-compatible, three-state I/O |
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• High speed |
• 28-pin JEDEC standard packages |
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- 12/15/20 ns address access time |
- 300 mil PDIP |
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- 5/6/7/9 ns output enable access time |
- 300 mil SOJ |
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• Very low power consumption: ACTIVE |
- 8 × 13.4 TSOP |
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- 660mW (AS7C256) / max @ 12 ns |
• ESD protection ≥ 2000 volts |
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- 216mW (AS7C3256) / max @ 12 ns |
• Latch-up current ≥ 200 mA |
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•Very low power consumption: STANDBY
- 22 mW (AS7C256) / max CMOS I/O
Logic block diagram |
Pin arrangement |
VCC
GND
A0
A1
A2
A3
A4
A5
A6
A14
Row decoder
Input buffer |
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I/O7 |
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256 X 128 X 8 |
amp |
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Array |
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Sense |
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(262,144) |
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I/O0 |
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Column decoder |
WE |
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Control |
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OE |
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circuit |
CE
A A A A A A A 7 8 9 10 11 12 13
28-pin TSOP I (8×13.4) |
28-pin DIP, SOJ (300 mil) |
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OE |
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1 |
(22) |
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(21) |
28 |
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A10 |
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A11 |
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2 |
(23) |
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(20) |
27 |
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CE |
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A9 |
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3 |
(24) |
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(19) |
26 |
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I/O7 |
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A8 |
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4 |
(25) |
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(18) |
25 |
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I/O6 |
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A13 |
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5 |
(26) |
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(17) |
24 |
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I/O5 |
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WE |
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6 |
(27) |
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(16) |
23 |
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I/O4 |
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VCC |
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7 |
(28) |
AS7C256 |
(15) |
22 |
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I/O3 |
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A14 |
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8 |
(1) |
AS7C3256 |
(14) |
21 |
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GND |
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A12 |
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9 |
(2) |
(13) |
20 |
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I/O2 |
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A7 |
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10 |
(3) |
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(12) |
19 |
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I/O1 |
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A6 |
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11 |
(4) |
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(11) |
18 |
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I/O0 |
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A5 |
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12 |
(5) |
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(10) |
17 |
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A0 |
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A4 |
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13 |
(6) |
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(9) |
16 |
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A1 |
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A3 |
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14 |
(7) |
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(8) |
15 |
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A2 |
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Note: This part is compatible with both pin numbering conventions used by various manufacturers.
A14 |
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1 |
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A12 |
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2 |
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A7 |
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3 |
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A6 |
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4 |
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A5 |
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5 |
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A4 |
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6 |
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A3 |
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7 |
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A2 |
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8 |
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A1 |
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9 |
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A0 |
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10 |
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I/O0 |
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11 |
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I/O1 |
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12 |
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I/O2 |
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13 |
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GND |
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14 |
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AS7C256 |
AS7C3256 |
28 VCC
27 WE
26 A13
25 A8
24 A9
23 A11
22 OE
21 A10
20 CE
19 I/O7
18 I/O6
17 I/O5
16 I/O4
15 I/O3
Selection guide
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AS7C256-10 |
AS7C256-12 |
AS7C256-15 |
AS7C256-20 |
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AS7C3256-10 |
AS7C3256-12 |
AS7C3256-15 |
AS7C3256-20 |
Unit |
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Maximum address access time |
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10 |
12 |
15 |
20 |
ns |
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Maximum output enable access time |
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5 |
6 |
7 |
ns |
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Maximum operating current |
AS7C256 |
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120 |
115 |
110 |
mA |
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AS7C3256 |
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60 |
55 |
50 |
mA |
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Maximum CMOS standby |
AS7C256 |
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4 |
4 |
4 |
mA |
current |
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AS7C3256 |
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2 |
2 |
2 |
mA |
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1/10/2001 |
Alliance Semiconductor |
P. 1 of 9 |
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Copyright © Alliance Semiconductor. All rights reserved.