Процедурное моделирование

Vhdl-проектов логических систем

entity KURS is

port(r1,c1,ec: in bit; q: out bit_vector(1 to 3); qo: inout bit);

end KURS;

library kunits;

use kunits.all;

architecture KROT of KURS is

component inv

port(x: in bit; y: out bit);

end component;

component sum

port(x,y: in bit; z: out bit);

end component;

component mnd

generic(m:natural:=2);

port(x: in bit_vector(1 to m); y: out bit);

end component;

component SDNCTT

port(s,d,c: in bit; q,nq: inout bit);

end component;

for all: sdnctt use entity kunits.sdnctt(behavior);

for all: inv use entity kunits.inv(beh);

for all: mnd use entity kunits.mnd(poh);

for all: sum use entity kunits.sum(sum_beh);

signal na,nb,nc : bit_vector(1 to 2);

signal k,a,b,d,h: bit;

begin

d1: inv port map(ec,a);

d2: sum port map(c1,a,b);

d3: inv port map(b,d);

d5: inv port map(qo,na(1));

d6: mnd port map(na(1),b,na(2));

d8: mnd generic map(3)

port map(nb(1),na(1),b,nb(2));

d10: mnd generic map(4)

port map(nc(1),nb(1),na(1),b,nc(2));

d4: SDNCTT port map(r1,h,d,qo,h);

d7: SDNCTT port map(r1,nb(1),na(2),q(1),nb(1));

d9: SDNCTT port map(r1,nc(1),nb(2),q(2),nc(1));

d11: SDNCTT port map(r1,k,nc(2),q(3),k);

end krot;

entity test is

end test;

library vector;

use std.textio.all;

architecture behavior of test is

component adder

port(r1,c1,ec: in bit; q: out bit_vector(1 to 3); qo: inout bit);

end component;

for all:adder use entity work.KURS(KROT);

signal ec,qo,r1,c1: bit;

signal q: bit_vector(1 to 3);

begin

krik:adder

port map(r1,c1,ec,qo,q);

process

begin

r1<=’1’, ‘0’after 5ns, '1'after 195ns;

c1<=’0’, ’1’after 10ns,’0’after 15ns,’1’after 20ns,’0’after 25ns,’1’after 30ns,’0’after 35ns,’1’after 40ns,’0’after 45ns,’1’after 50ns,’0’after 55ns,’1’after 60ns,’0’after 65ns,’1’after 70ns,’0’after 75ns,’1’after 80ns,’0’after 85ns,’1’after 90ns,’0’after 95ns, ’1’after 100ns,’0’after 105ns;

ec<=’1’, ’0’after 110ns,’1’after 115ns,’0’after 120ns,’1’after 125ns,’0’after 130ns,’1’after 135ns,’0’after 140ns,’1’after 145ns,’0’after 150ns,’1’after 155ns,’0’after 160ns,’1’after 165ns,’0’after 170ns,’1’after 175ns,’0’after 180ns,’1’after 185ns,’0’after 190ns;

wait;

end process;

p2: process

variable ll: line;

variable f: integer:=0;

variable t,k:time;

begin

t:=now;

if (t=2.5ns) then

if f=0 then

write(ll,"time r1 c1 ec q0 q1 q2 q3");writeline(output,ll);

f:=1;

end if; end if;

k:=7.5ns;

if (t=k) then

write(ll,k);write(ll," ");write(ll,r1);write(ll," ");

write(ll,c1);write(ll," ");write(ll,ec);write(ll," ");

write(ll,qo);write(ll," ");write(ll,q(1));

write(ll,q(2));write(ll," ");write(ll,q(3));

writeline(output,ll);

k:=k+5ns;

end if;

wait for 2.5ns;

end process;

end;

ТАБЛИЦА ИСТИННОСТИ

TIME r1 c1 ec q0 q1 q2 q3

2.5Ns 1 0 1 0 0 0 0

7.5ns 0 0 1 0 0 0 0

12.5ns 0 1 1 1 0 0 0

17.5ns 0 0 1 1 0 0 0

22.5ns 0 1 1 0 1 0 0

27.5ns 0 0 1 0 1 0 0

32.5ns 0 1 1 1 1 0 0

37.5ns 0 0 1 1 1 0 0

42.5ns 0 1 1 0 0 1 0

47.5ns 0 0 1 0 0 1 0

52.5ns 0 1 1 1 0 1 0

57.5ns 0 0 1 1 0 1 0

62.5ns 0 1 1 0 1 1 0

67.5ns 0 0 1 0 1 1 0

72.5ns 0 1 1 1 1 1 0

77.5ns 0 0 1 1 1 1 0

82.5ns 0 1 1 0 0 0 1

87.5ns 0 0 1 0 0 0 1

92.5ns 0 1 1 1 0 0 1

97.5ns 0 0 1 1 0 0 1

102.5ns 0 1 1 0 1 0 1

107.5ns 0 0 1 0 1 0 1

112.5ns 0 0 0 1 1 0 1

117.5ns 0 0 1 1 1 0 1

122.5ns 0 0 0 0 0 1 1

127.5ns 0 0 1 0 0 1 1

132.5ns 0 0 0 1 0 1 1

137.5ns 0 0 1 1 0 1 1

142.5ns 0 0 0 0 1 1 1

147.5ns 0 0 1 0 1 1 1

152.5ns 0 0 0 1 1 1 1

157.5ns 0 0 1 1 1 1 1

162.5ns 0 0 0 0 0 0 0

167.5ns 0 0 1 0 0 0 0

172.5ns 0 0 0 1 0 0 0

177.5ns 0 0 1 1 0 0 0

182.5ns 0 0 0 0 1 0 0

187.5ns 0 0 1 0 1 0 0

192.5ns 0 0 0 1 1 0 0

197.5ns 1 0 0 0 0 0 0

Интерактивно-графическое моделирование

VHDL-проектов логических систем

Регрессионный тест структурной и регистровой архитектур

Если сигналы на выходах структурной и регистровой архитектур при тесте не будут совпадать то появится сообщение об ошибке «severity error»!

library kursovik;

use kursovik.all;

entity test is

end test;

architecture beh_t of test is

component test1

port(r1,c1,ec: in bit; q: out bit_vector(1 to 3); qo: inout bit);

end component;

component test2

port(r1,c1,ec: in bit; q: out bit_vector(1 to 3); qo: inout bit);

end component;

for all: test1 use entity kursovik.kurs(krot);

for all: test2 use entity kursovik.kurs(lis);

signal c1,ec,r1:bit;

signal q,q1:bit_vector(1 to 3);

signal qo,qo1:bit;

begin

a1:test1 port map(r1,c1,ec,q,qo);

a2:test2 port map(r1,c1,ec,q1,qo1);

process(qo,qo1,q,q1)

begin

assert qo=qo1 report "qo/=qo1" severity error;

for i in 1 to 3 loop

assert q(i)=q1(i) report "q/=q1" severity error;

end loop;

end process;

end beh_t;