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        1. Stop the clocks

Where SMT offers chip designers a big performance gain for a relatively small design change, asynchronous logic involves a far more dramatic rethink. As its name suggests, it does away with the cardinal rule of chip design: that everything marches to the beat of an oscillating crystal “clock”. For a 1GHz chip, this clock ticks one billion times a second, and all of the chip’s processing units co-ordinate their actions with these ticks to ensure that they remain in step. Asynchronous, or “clockless”, designs, in contrast, allow different bits of a chip to work at different speeds, sending data to and from each other as and when appropriate.

The idea of asynchronous logic goes back to the dawn of digital computers. Some of the earliest machines (built in the 1950s) were based on clockless designs. But the synchronous approach predominated, largely because it is easier to design chips in which things happen only when the clock ticks. In recent years, however, clockless designs have started to look more appealing. One reason is that, as chips get bigger, faster and more complicated, distributing the clock signal around the chip becomes harder. Another drawback with clocked designs is that they waste a lot of energy, since even inactive parts of the chip have to respond to every clock tick. Clocked chips also produce electromagnetic emissions at their clock frequency, which can cause radio interference.

There are several styles of asynchronous design, according to Steve Furber, a computer scientist at Manchester University in Britain. Whereas conventional chips represent the zeroes and ones of binary digits (“bits”) using low and high voltages on a particular wire, one clockless approach, called “dual rail”, uses two wires for each bit. A sudden voltage change on one of the wires represents a zero, and on the other wire a one. Another approach is called “bundled data”. Low and high voltages on 32 wires are used to represent 32 bits, and a change in voltage on a 33rd wire indicates when the values on the other 32 wires are to be used.

Asynchronous designs take up more room on a chip than conventional designs, and there are far fewer design tools available to help create them, but a number of groups, including Dr Furber’s, have already built asynchronous microprocessors. Ivan Sutherland of Sun Microsystems, who is regarded as the guru of the field, believes that such chips will have twice the power of conventional designs, which will make them ideal for use in high-performance computers. But Dr Furber suggests that the most promising application for asynchronous chips may be in mobile wireless devices and smartcards.

Wireless devices based on asynchronous chips would run for longer between recharges, and their circuitry would cause less radio interference. Dr Furber is developing asynchronous chips for such devices in conjunction with ARM, a British company whose processors appear in many handheld computers and mobile phones. Philips, a Dutch electronics firm, has already built a pager that uses asynchronous logic, and Theseus Logic of Orlando, Florida, is also pursuing low-power wireless applications.

In the case of smartcards, Dr Furber suggests that asynchronous logic would offer better security than conventional chips. The encryption on existing smartcards can be cracked by analysing the power consumption for each clock tick. This allows details of the chip’s inner workings to be deduced. Such an attack would be far more difficult on a smartcard based on asynchronous logic.

There is, of course, a catch. Both SMT and asynchronous logic undermine the use of a chip’s clock speed as a proxy for its performance. And that might make things tricky for the marketing men, who have long insisted that the more MHz, the merrier.

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