Ординатура / Хирургия / Библиотека им академика М.И. Перельмана / Книга_3835_Библиотеки_им_академика_М_И_Перельмана

analog filter has been applied before the ADC, there are still some noises left that get into the digital circuits. A digital filter in the FPGA would eliminate the undesirable noises and improve the SNR further. The easiest way in FPGA for the filter is FIR filter (Qiu et al. 2012). Since FPGA is competent for multiplication and addition, it is very suitable for the FIR calculation. Moreover, the FIR filter coefficients are symmetric; therefore, the number of multipliers can be reduced by half, which saves resources in the FPGA. Some advanced functions such as DSP block in the FPGA can be used to achieve fast processing. Although high order FIR provides better noise suppression, it results in elongated ripples which degraded the imaging resolution. Therefore, it is a trade-off for the selection of SNR improvement and unwanted ripples. Figure 11.6 shows a representative signal processed by a digital 31-tap FIR band-pass filter. More than 40 dB additional noise suppression can be attained with this setting. FPGA also supports high-speed process, which the FIR filter can run in a clock higher than 240 MHz. The coefficients of the digital filter are flexible and reconfigurable during the imaging process.

Grayscale B-mode imaging is usually used for the IVUS imaging to represent the backscattering of the ultrasound from the vessel. It requires a positive data for the display. Usually, the envelope is extracted from the filtered ultrasound data. Since ultrasound echo signals are broadband in frequency spectrum, the Hilbert transform could be used to extract the envelope. An architectural example of the envelope detection method is shown in Fig. 11.7. The in-phase (I) and quadrature (Q) signal could be obtained by the Hilbert transform. The modulus of I/Q signals is calculated for the acquisition of envelope by removing the carrier frequency. To fit for FPGA architecture, cordic algorithm could be employed for this action by an iterative pro­cess using a series of adders and shifters (Qiu et al. 2012). Simulation with cordic algorithm in the FPGA shows that it can run at a 250 MHz clock, which supports a high throughput process for modulus calculation.

A single element transducer is usually employed for IVUS imaging, which requires a mechanical rotation of the transducer to acquire a sectional image. Therefore, the ultrasound signals are obtained at different angles (~500 angles), which restores as a polar coordinate. On the other hand, the screen for the imaging is presented with Cartesian coordinates. So that, a conversion named as digital scan convertor (DSC) is required to transform the polar coordinate’s data to Cartesian coordinate’s data (Chang et al. 2008; Levesque and Sawan 2009). Figure 11.8 demonstrates the principle of DSC. C-R represents the Cartesian coordinate and P represents the Polar coordinate. The value in pixel S can be calculated by relevant P interpolation can be achieved in the FPGA (Qiu et al. 2012).