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<Описание устройства>

Разработанная FSM Diagram

<диаграмма>

Описание на Verilog (сгенерированный код)

<Код>

module lift (

clock,reset,ctrl,updon,

evnt[2:0]);

input clock;

input reset;

input ctrl;

input updon;

tri0 reset;

tri0 ctrl;

tri0 updon;

output [2:0] evnt;

reg [2:0] evnt;

reg [4:0] fstate;

reg [4:0] reg_fstate;

parameter knop=0,up=1,don=2,goup=3,godon=4;

always @(posedge clock or posedge reset)

begin

if (reset) begin

fstate <= knop;

end

else begin

fstate <= reg_fstate;

end

end

always @(fstate or ctrl or updon)

begin

evnt <= 3'b000;

case (fstate)

knop: begin

if (updon)

reg_fstate <= up;

else if (~(updon))

reg_fstate <= don;

// Inserting 'else' block to prevent latch inference

else

reg_fstate <= knop;

evnt <= 3'b000;

end

up: begin

reg_fstate <= godon;

evnt <= 3'b001;

end

don: begin

reg_fstate <= goup;

evnt <= 3'b010;

end

goup: begin

if ((ctrl | ~(ctrl)))

reg_fstate <= goup;

// Inserting 'else' block to prevent latch inference

else

reg_fstate <= goup;

evnt <= 3'b011;

end

godon: begin

if ((ctrl | ~(ctrl)))

reg_fstate <= godon;

// Inserting 'else' block to prevent latch inference

else

reg_fstate <= godon;

evnt <= 3'b100;

end

default: begin

evnt <= 3'bxxx;

$display ("Reach undefined state");

end

endcase

end

endmodule // lift

RTL-схема

<RTL-схема>

FSM-диаграмма

Временная диаграмма